u-boot/arch/x86/dts/coreboot.dts
Bin Meng 864915561b x86: coreboot: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:49 +08:00

45 lines
675 B
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*
* Generic coreboot payload device tree for x86 targets
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
compatible = "coreboot,x86-payload";
aliases {
serial0 = &serial;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
};
coreboot-fb {
compatible = "coreboot-fb";
};
};