mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
4d9253fb76
For the RK3188, the BROM will attempt to load up the first stage image (SPL for the RK3188) in two steps: first 1KB to offset 0x800 in the SRAM and then the remainder to offset 0xc00 in the SRAM. It always enters at 0x804, though. With this changeset, the RK3188 boot removes the TPL (stub) stage and builds a single SPL binary that utilizes the early back-to-bootrom via the boot0-hook. Consequently, the passing of the saved boot params via pmu->os_reg[2] is also removed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3188_COMMON_H
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#define __CONFIG_RK3188_COMMON_H
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#include <asm/arch/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
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#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_NS16550_MEM32
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#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
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#define CONFIG_SPL_TEXT_BASE 0x10080800
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/* spl size 32kb sram - 2kb bootrom */
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#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
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#define CONFIG_SPL_FRAMEWORK 1
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#define CONFIG_SPL_CLK 1
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#define CONFIG_SPL_PINCTRL 1
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#define CONFIG_SPL_REGMAP 1
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#define CONFIG_SPL_SYSCON 1
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#define CONFIG_SPL_RAM 1
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
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#define CONFIG_ROCKCHIP_SERIAL 1
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#define CONFIG_SPL_STACK 0x10087fff
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/* MMC/SD IP block */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define CONFIG_NR_DRAM_BANKS 1
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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/* usb otg */
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#define CONFIG_ROCKCHIP_USB2_PHY
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/* usb host support */
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x60000000\0" \
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"pxefile_addr_r=0x60100000\0" \
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"fdt_addr_r=0x61f00000\0" \
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"kernel_addr_r=0x62000000\0" \
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"ramdisk_addr_r=0x64000000\0"
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
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* so limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x6fffffff\0" \
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"initrd_high=0x6fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_PREBOOT
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#endif
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