mirror of
https://github.com/AsahiLinux/u-boot
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fdce83c108
Take the cache flush functions from the kernel as they use hardware loops in order to get optimal performance. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
71 lines
1.3 KiB
C
71 lines
1.3 KiB
C
/*
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* U-boot - cache.c
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/mpu.h>
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void flush_cache(unsigned long addr, unsigned long size)
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{
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void *start_addr, *end_addr;
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int istatus, dstatus;
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/* no need to flush stuff in on chip memory (L1/L2/etc...) */
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if (addr >= 0xE0000000)
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return;
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start_addr = (void *)addr;
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end_addr = (void *)(addr + size);
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istatus = icache_status();
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dstatus = dcache_status();
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if (istatus) {
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if (dstatus)
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blackfin_icache_dcache_flush_range(start_addr, end_addr);
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else
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blackfin_icache_flush_range(start_addr, end_addr);
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} else if (dstatus)
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blackfin_dcache_flush_range(start_addr, end_addr);
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}
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void icache_enable(void)
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{
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bfin_write_IMEM_CONTROL(IMC | ENICPLB);
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SSYNC();
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}
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void icache_disable(void)
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{
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bfin_write_IMEM_CONTROL(0);
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SSYNC();
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}
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int icache_status(void)
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{
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return bfin_read_IMEM_CONTROL() & IMC;
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}
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void dcache_enable(void)
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{
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bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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SSYNC();
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}
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void dcache_disable(void)
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{
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bfin_write_DMEM_CONTROL(0);
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SSYNC();
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}
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int dcache_status(void)
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{
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return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
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}
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