mirror of
https://github.com/AsahiLinux/u-boot
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2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
2 KiB
C
92 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/eagle/eagle.c
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* This file is Eagle board support.
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <init.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPR 0xE6150900
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#define CPGWPCR 0xE6150904
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/* PLL */
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#define PLL0CR 0xE61500D8
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#define PLL0_STC_MASK 0x7F000000
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#define PLL0_STC_OFFSET 24
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 0.8GHz */
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stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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}
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int board_early_init_f(void)
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{
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/* Unlock CPG access */
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writel(0xA5A5FFFF, CPGWPR);
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writel(0x5A5A0000, CPGWPCR);
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_RSTOUTCR (RST_BASE + 0x58)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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void reset_cpu(void)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else if (cputype == 0xd07)
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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else
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hang();
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}
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