Masahiro Yamada 9c2f9b2da6 ARM: uniphier: insert dsb barrier to ensure visibility of store ... I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>		2016-06-09 08:19:13 +09:00
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arm-cci500.c	ARM: uniphier: add PH1-LD20 SoC support	2016-04-24 09:54:08 +09:00
Makefile	ARM: uniphier: add PH1-LD20 SoC support	2016-04-24 09:54:08 +09:00
mem_map.c	ARM: uniphier: add PH1-LD20 SoC support	2016-04-24 09:54:08 +09:00
smp.S	ARM: uniphier: add PH1-LD20 SoC support	2016-04-24 09:54:08 +09:00
smp_kick_cpus.c	ARM: uniphier: insert dsb barrier to ensure visibility of store	2016-06-09 08:19:13 +09:00
timer.c	ARM: uniphier: add PH1-LD20 SoC support	2016-04-24 09:54:08 +09:00