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https://github.com/AsahiLinux/u-boot
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4c56d75117
The 4.6 spec added an upper 32bits to the ATU limit, and since this driver is already assuming the unrolled feature added in the 4.8 specification this really should be set. This is causing a bug with testing against the QEMU model as it defaults the viewports to fully open and not setting this causes the config viewport to become most of memory (obviously stopping the emulated system working correctly) Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
371 lines
11 KiB
C
371 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2021 Rockchip, Inc.
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*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pci.h>
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#include <dm/device_compat.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "pcie_dw_common.h"
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int pcie_dw_get_link_speed(struct pcie_dw *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
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}
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int pcie_dw_get_link_width(struct pcie_dw *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
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}
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static void dw_pcie_writel_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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writel(val, base + offset + reg);
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}
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static u32 dw_pcie_readl_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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return readl(base + offset + reg);
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}
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/**
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* pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
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*
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* @pcie: Pointer to the PCI controller state
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* @index: ATU region index
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* @type: ATU accsess type
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* @cpu_addr: the physical address for the translation entry
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* @pci_addr: the pcie bus address for the translation entry
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* @size: the size of the translation entry
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*
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* Return: 0 is successful and -1 is failure
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*/
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int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
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int type, u64 cpu_addr,
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u64 pci_addr, u32 size)
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{
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u32 retries, val;
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dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
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index, type, cpu_addr, pci_addr, size);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
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upper_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
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type);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ob_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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udelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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return -1;
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}
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/**
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* set_cfg_address() - Configure the PCIe controller config space access
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*
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* @pcie: Pointer to the PCI controller state
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* @d: PCI device to access
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* @where: Offset in the configuration space
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*
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* Configures the PCIe controller to access the configuration space of
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* a specific PCIe device and returns the address to use for this
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* access.
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*
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* Return: Address that can be used to access the configation space
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* of the requested device / offset
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*/
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static uintptr_t set_cfg_address(struct pcie_dw *pcie,
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pci_dev_t d, uint where)
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{
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int bus = PCI_BUS(d) - pcie->first_busno;
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uintptr_t va_address;
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u32 atu_type;
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int ret;
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/* Use dbi_base for own configuration read and write */
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if (!bus) {
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va_address = (uintptr_t)pcie->dbi_base;
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goto out;
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}
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if (bus == 1)
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/*
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* For local bus whose primary bus number is root bridge,
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* change TLP Type field to 4.
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*/
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atu_type = PCIE_ATU_TYPE_CFG0;
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else
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/* Otherwise, change TLP Type field to 5. */
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atu_type = PCIE_ATU_TYPE_CFG1;
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/*
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* Not accessing root port configuration space?
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* Region #0 is used for Outbound CFG space access.
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* Direction = Outbound
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* Region Index = 0
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*/
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d = PCI_MASK_BUS(d);
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d = PCI_ADD_BUS(bus, d);
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ret = pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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atu_type, (u64)pcie->cfg_base,
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d << 8, pcie->cfg_size);
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if (ret)
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return (uintptr_t)ret;
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va_address = (uintptr_t)pcie->cfg_base;
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out:
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va_address += where & ~0x3;
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return va_address;
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}
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/**
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* pcie_dw_addr_valid() - Check for valid bus address
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*
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* @d: The PCI device to access
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* @first_busno: Bus number of the PCIe controller root complex
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*
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* Return 1 (true) if the PCI device can be accessed by this controller.
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*
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* Return: 1 on valid, 0 on invalid
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*/
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static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
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{
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if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
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return 0;
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if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
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return 0;
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return 1;
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}
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/**
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* pcie_dw_read_config() - Read from configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct pcie_dw *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong value;
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dev_dbg(pcie->dev, "PCIE CFG read: bdf=%2x:%2x:%2x ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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*valuep = pci_get_ff(size);
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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value = readl((void __iomem *)va_address);
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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*valuep = pci_conv_32_to_size(value, offset, size);
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return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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}
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/**
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* pcie_dw_write_config() - Write to configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_dw *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong old;
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dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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dev_dbg(pcie->dev, "(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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old = readl((void __iomem *)va_address);
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value = pci_conv_size_to_32(old, value, offset, size);
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writel(value, (void __iomem *)va_address);
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return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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}
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/**
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* pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
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*
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* @pcie: Pointer to the PCI controller state
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*
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* Configure the host BARs of the PCIe controller root port so that
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* PCI(e) devices may access the system memory.
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*/
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void pcie_dw_setup_host(struct pcie_dw *pci)
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{
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struct udevice *ctlr = pci_get_controller(pci->dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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u32 ret;
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if (!pci->atu_base)
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pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
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/* setup RC BARs */
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writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
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pci->dbi_base + PCI_BASE_ADDRESS_0);
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writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
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/* setup interrupt pins */
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clrsetbits_le32(pci->dbi_base + PCI_INTERRUPT_LINE,
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0xff00, 0x100);
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/* setup bus numbers */
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clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
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0xffffff, 0x00ff0100);
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/* setup command register */
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clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
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0xffff,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
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/* Enable write permission for the DBI read-only register */
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dw_pcie_dbi_write_enable(pci, true);
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/* program correct class for RC */
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writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
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/* Better disable write permission right after the update */
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dw_pcie_dbi_write_enable(pci, false);
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setbits_le32(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL,
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PORT_LOGIC_SPEED_CHANGE);
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for (ret = 0; ret < hose->region_count; ret++) {
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if (hose->regions[ret].flags == PCI_REGION_IO) {
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pci->io.phys_start = hose->regions[ret].phys_start; /* IO base */
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pci->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */
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pci->io.size = hose->regions[ret].size; /* IO size */
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} else if (hose->regions[ret].flags == PCI_REGION_MEM) {
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pci->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */
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pci->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */
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pci->mem.size = hose->regions[ret].size; /* MEM size */
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} else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) {
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pci->prefetch.phys_start = hose->regions[ret].phys_start; /* PREFETCH base */
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pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */
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pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */
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} else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
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pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size);
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pci->cfg_size = pci->io.size;
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} else {
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dev_err(pci->dev, "invalid flags type!\n");
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}
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}
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dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size,
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(u64)pci->cfg_size);
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dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size,
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(u64)pci->io.size);
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dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size,
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(u64)pci->io.size);
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dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->mem.phys_start,
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(u64)pci->mem.phys_start + pci->mem.size,
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(u64)pci->mem.size);
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dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->mem.bus_start,
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(u64)pci->mem.bus_start + pci->mem.size,
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(u64)pci->mem.size);
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if (pci->prefetch.size) {
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dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->prefetch.phys_start,
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(u64)pci->prefetch.phys_start + pci->prefetch.size,
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(u64)pci->prefetch.size);
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dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size 0x%llx]\n",
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(u64)pci->prefetch.bus_start,
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(u64)pci->prefetch.bus_start + pci->prefetch.size,
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(u64)pci->prefetch.size);
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}
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}
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