mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
385 lines
7.9 KiB
C
385 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ppa.h>
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#include <asm/arch/fdt.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/soc.h>
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#include <ahci.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <spl.h>
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#include "../common/qixis.h"
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#include "ls1043aqds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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MUX_TYPE_GPIO,
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};
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/* LS1043AQDS serdes mux */
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#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
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#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
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#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
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#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
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#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
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#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
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#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
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#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
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#define CFG_UART_MUX_MASK 0x6
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#define CFG_UART_MUX_SHIFT 1
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#define CFG_LPUART_EN 0x1
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int checkboard(void)
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{
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char buf[64];
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#ifndef CONFIG_SD_BOOT
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u8 sw;
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#endif
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puts("Board: LS1043AQDS, boot from ");
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#ifdef CONFIG_SD_BOOT
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puts("SD\n");
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#else
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0xF)
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printf("QSPI\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
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QIXIS_READ(id), QIXIS_READ(arch));
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printf("FPGA: v%d (%s), build %d\n",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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return 0;
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}
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bool if_board_diff_clk(void)
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{
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u8 diff_conf = QIXIS_READ(brdcfg[11]);
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return diff_conf & 0x40;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_64:
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return 64000000;
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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if (if_board_diff_clk())
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return get_board_sys_clk();
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int dram_init(void)
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{
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/*
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* When resuming from deep sleep, the I2C channel may not be
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* in the default channel. So, switch to the default channel
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* before accessing DDR SPD.
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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fsl_initdram();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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#endif
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return 0;
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}
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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return select_i2c_ch_pca9547(channel);
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}
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void board_retimer_init(void)
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{
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u8 reg;
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/* Retimer is connected to I2C1_CH7_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH7);
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reg = I2C_MUX_CH5;
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i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
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/* Access to Control/Shared register */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Read device revision and ID */
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Reset Channel Registers */
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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reg |= 0x4;
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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/* Enable override divider select and Enable Override Output Mux */
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i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
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reg |= 0x24;
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i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
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/* Select VCO Divider to full rate (000) */
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i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
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reg &= 0x8f;
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i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
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/* Selects active PFD MUX Input as Re-timed Data (001) */
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i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
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reg &= 0x3f;
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reg |= 0x20;
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i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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reg = 0xb2;
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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/* Return the default channel */
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 usb_pwrfault;
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#endif
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#ifdef CONFIG_LPUART
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u8 uart;
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#endif
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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#endif
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fsl_lsch2_early_init_f();
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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out_be32(&scfg->rcwpmuxcr0, 0x3333);
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out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
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usb_pwrfault =
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(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
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out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
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#endif
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#ifdef CONFIG_LPUART
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/* We use lpuart0 as system console */
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uart = QIXIS_READ(brdcfg[14]);
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uart &= ~CFG_UART_MUX_MASK;
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uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
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QIXIS_WRITE(brdcfg[14], uart);
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#endif
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return 0;
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}
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#ifdef CONFIG_FSL_DEEP_SLEEP
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/* determine if it is a warm boot */
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bool is_warm_boot(void)
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{
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#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
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return 1;
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return 0;
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}
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#endif
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int config_board_mux(int ctrl_type)
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{
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u8 reg14;
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reg14 = QIXIS_READ(brdcfg[14]);
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switch (ctrl_type) {
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case MUX_TYPE_GPIO:
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reg14 = (reg14 & (~0x30)) | 0x20;
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break;
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default:
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puts("Unsupported mux interface type\n");
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return -1;
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}
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QIXIS_WRITE(brdcfg[14], reg14);
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return 0;
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}
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int config_serdes_mux(void)
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{
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return 0;
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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if (hwconfig("gpio"))
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config_board_mux(MUX_TYPE_GPIO);
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return 0;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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board_retimer_init();
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#ifdef CONFIG_SYS_FSL_SERDES
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config_serdes_mux();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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u8 reg;
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/* fixup DT for the two DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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reg = QIXIS_READ(brdcfg[0]);
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reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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/* Disable IFC if QSPI is enabled */
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if (reg == 0xF)
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do_fixup_by_compat(blob, "fsl,ifc",
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"status", "disabled", 8 + 1, 1);
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return 0;
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}
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#endif
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u8 flash_read8(void *addr)
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{
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return __raw_readb(addr + 1);
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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