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34196b0a8b
Replace call to imx_get_mpllclk with imx_get_armclk to show frequency of ARM core instead of mpll internal bus in print_cpuinfo. Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Stefano Babic <sbabic@denx.de>
263 lines
6.5 KiB
C
263 lines
6.5 KiB
C
/*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on mx27/generic.c:
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* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <div64.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx25-pinmux.h>
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#ifdef CONFIG_MXC_MMC
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#include <asm/arch/mxcmmc.h>
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#endif
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/*
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* get the system pll clock in Hz
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*
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* mfi + mfn / (mfd +1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
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{
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unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
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& CCM_PLL_MFI_MASK;
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unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
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& CCM_PLL_MFN_MASK;
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unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
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& CCM_PLL_MFD_MASK;
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unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
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& CCM_PLL_PD_MASK;
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mfi = mfi <= 5 ? 5 : mfi;
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return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
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(mfd + 1) * (pd + 1));
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}
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static ulong imx_get_mpllclk (void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = 24000000;
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return imx_decode_pll (readl (&ccm->mpctl), fref);
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}
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ulong imx_get_armclk (void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong cctl = readl (&ccm->cctl);
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ulong fref = imx_get_mpllclk ();
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ulong div;
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if (cctl & CCM_CCTL_ARM_SRC)
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fref = lldiv ((fref * 3), 4);
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div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
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& CCM_CCTL_ARM_DIV_MASK) + 1;
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return lldiv (fref, div);
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}
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ulong imx_get_ahbclk (void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong cctl = readl (&ccm->cctl);
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ulong fref = imx_get_armclk ();
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ulong div;
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div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
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& CCM_CCTL_AHB_DIV_MASK) + 1;
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return lldiv (fref, div);
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}
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ulong imx_get_perclk (int clk)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = imx_get_ahbclk ();
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ulong div;
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div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
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div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
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return lldiv (fref, div);
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo (void)
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{
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char buf[32];
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printf ("CPU: Freescale i.MX25 at %s MHz\n\n",
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strmhz (buf, imx_get_armclk ()));
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return 0;
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}
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#endif
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int cpu_eth_init (bd_t * bis)
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{
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#if defined(CONFIG_FEC_MXC)
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong val;
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val = readl (&ccm->cgr0);
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val |= (1 << 23);
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writel (val, &ccm->cgr0);
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return fecmxc_initialize (bis);
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#else
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return 0;
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#endif
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}
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init (bd_t * bis)
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{
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#ifdef CONFIG_MXC_MMC
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return mxc_mmc_init (bis);
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#else
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return 0;
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#endif
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}
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#ifdef CONFIG_MXC_UART
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void mx25_uart_init_pins (void)
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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u32 inpadctl;
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u32 outpadctl;
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u32 muxmode0;
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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muxmode0 = MX25_PIN_MUX_MODE (0);
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/*
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* set up input pins with hysteresis and 100K pull-ups
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*/
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inpadctl = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
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/*
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* set up output pins with 100K pull-downs
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* FIXME: need to revisit this
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* PUE is ignored if PKE is not set
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* so the right value here is likely
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* 0x0 for no pull up/down
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* or
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* 0xc0 for 100k pull down
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*/
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outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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/* UART1 */
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/* rxd */
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writel (muxmode0, &muxctl->pad_uart1_rxd);
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writel (inpadctl, &padctl->pad_uart1_rxd);
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/* txd */
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writel (muxmode0, &muxctl->pad_uart1_txd);
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writel (outpadctl, &padctl->pad_uart1_txd);
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/* rts */
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writel (muxmode0, &muxctl->pad_uart1_rts);
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writel (outpadctl, &padctl->pad_uart1_rts);
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/* cts */
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writel (muxmode0, &muxctl->pad_uart1_cts);
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writel (inpadctl, &padctl->pad_uart1_cts);
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}
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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void mx25_fec_init_pins (void)
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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u32 inpadctl_100kpd;
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u32 inpadctl_22kpu;
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u32 outpadctl;
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u32 muxmode0;
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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muxmode0 = MX25_PIN_MUX_MODE (0);
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inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
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/*
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* set up output pins with 100K pull-downs
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* FIXME: need to revisit this
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* PUE is ignored if PKE is not set
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* so the right value here is likely
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* 0x0 for no pull
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* or
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* 0xc0 for 100k pull down
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*/
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outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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/* FEC_TX_CLK */
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writel (muxmode0, &muxctl->pad_fec_tx_clk);
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writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
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/* FEC_RX_DV */
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writel (muxmode0, &muxctl->pad_fec_rx_dv);
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writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
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/* FEC_RDATA0 */
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writel (muxmode0, &muxctl->pad_fec_rdata0);
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writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
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/* FEC_TDATA0 */
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writel (muxmode0, &muxctl->pad_fec_tdata0);
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writel (outpadctl, &padctl->pad_fec_tdata0);
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/* FEC_TX_EN */
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writel (muxmode0, &muxctl->pad_fec_tx_en);
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writel (outpadctl, &padctl->pad_fec_tx_en);
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/* FEC_MDC */
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writel (muxmode0, &muxctl->pad_fec_mdc);
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writel (outpadctl, &padctl->pad_fec_mdc);
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/* FEC_MDIO */
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writel (muxmode0, &muxctl->pad_fec_mdio);
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writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
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/* FEC_RDATA1 */
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writel (muxmode0, &muxctl->pad_fec_rdata1);
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writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
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/* FEC_TDATA1 */
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writel (muxmode0, &muxctl->pad_fec_tdata1);
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writel (outpadctl, &padctl->pad_fec_tdata1);
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}
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#endif /* CONFIG_FEC_MXC */
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