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4b4159d0f3
There are two revisions of unmatched board with different DDR timing, we'd like to support multi-dtb mechanism in SPL, then it selects the right DTB at runtime according to PCB revision in I2C EEPROM. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
109 lines
2.3 KiB
C
109 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2020-2021 SiFive, Inc
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <init.h>
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#include <spl.h>
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#include <misc.h>
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#include <log.h>
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#include <fdtdec.h>
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#include <dm/root.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/eeprom.h>
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#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
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#define MODE_SELECT_REG 0x1000
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#define MODE_SELECT_SD 0xb
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#define MODE_SELECT_MASK GENMASK(3, 0)
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int spl_board_init_f(void)
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{
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int ret;
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
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int rescan;
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ret = fdtdec_resetup(&rescan);
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if (!ret && rescan) {
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dm_uninit();
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dm_init_and_scan(true);
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}
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#endif
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ret = spl_soc_init();
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if (ret) {
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debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
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return ret;
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}
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/*
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* GEMGXL init VSC8541 PHY reset sequence;
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* leave pull-down active for 2ms
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*/
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udelay(2000);
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ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
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if (ret) {
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debug("gem_phy_reset gpio request failed: %d\n", ret);
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return ret;
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}
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/* Set GPIO 12 (PHY NRESET) */
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ret = gpio_direction_output(GEM_PHY_RESET, 1);
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if (ret) {
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debug("gem_phy_reset gpio direction set failed: %d\n", ret);
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return ret;
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}
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udelay(1);
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/* Reset PHY again to enter unmanaged mode */
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gpio_set_value(GEM_PHY_RESET, 0);
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udelay(1);
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gpio_set_value(GEM_PHY_RESET, 1);
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mdelay(15);
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return 0;
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}
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u32 spl_boot_device(void)
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{
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u32 mode_select = readl((void *)MODE_SELECT_REG);
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u32 boot_device = mode_select & MODE_SELECT_MASK;
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switch (boot_device) {
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case MODE_SELECT_SD:
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return BOOT_DEVICE_MMC1;
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default:
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debug("Unsupported boot device 0x%x but trying MMC1\n",
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boot_device);
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return BOOT_DEVICE_MMC1;
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}
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/*
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* Apply different DDR params on different board revision.
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* Use PCB revision which is byte 0x7 in I2C platform EEPROM
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* to distinguish that.
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*/
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if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 &&
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!strcmp(name, "hifive-unmatched-a00"))
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return 0;
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else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 &&
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!strcmp(name, "hifive-unmatched-a00-rev1"))
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return 0;
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return -1;
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}
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#endif
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