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https://github.com/AsahiLinux/u-boot
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819833af39
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Reset Controller (RSTC) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_RSTC_H
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#define AT91_RSTC_H
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#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08)
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#ifndef __ASSEMBLY__
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typedef struct at91_rstc {
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u32 cr; /* Reset Controller Control Register */
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u32 sr; /* Reset Controller Status Register */
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u32 mr; /* Reset Controller Mode Register */
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} at91_rstc_t;
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#endif /* __ASSEMBLY__ */
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#define AT91_RSTC_KEY 0xA5000000
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#define AT91_RSTC_CR_PROCRST 0x00000001
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#define AT91_RSTC_CR_PERRST 0x00000004
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#define AT91_RSTC_CR_EXTRST 0x00000008
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#define AT91_RSTC_MR_URSTEN 0x00000001
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#define AT91_RSTC_MR_URSTIEN 0x00000010
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#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8)
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#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00
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#define AT91_RSTC_SR_NRSTL 0x00010000
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
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#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
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#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
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#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
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#define AT91_RSTC_RSTTYP_USER (4 << 8)
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#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
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#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
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#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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#endif /* CONFIG_AT91_LEGACY */
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#endif
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