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The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time. The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* D1/R528/T113 DRAM controller register and constant defines
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*
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* (C) Copyright 2022 Arm Ltd.
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* Based on H6 and H616 header, which are:
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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*/
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#ifndef _SUNXI_DRAM_SUN20I_D1_H
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#define _SUNXI_DRAM_SUN20I_D1_H
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enum sunxi_dram_type {
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SUNXI_DRAM_TYPE_DDR2 = 2,
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SUNXI_DRAM_TYPE_DDR3 = 3,
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SUNXI_DRAM_TYPE_LPDDR2 = 6,
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SUNXI_DRAM_TYPE_LPDDR3 = 7,
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};
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/*
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* This structure contains a mixture of fixed configuration settings,
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* variables that are used at runtime to communicate settings between
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* different stages and functions, and unused values.
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* This is copied from Allwinner's boot0 data structure, which can be
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* found at offset 0x38 in any boot0 binary. To allow matching up some
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* board specific settings, this struct is kept compatible, even though
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* we don't need all members in our code.
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*/
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typedef struct dram_para {
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/* normal configuration */
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const u32 dram_clk;
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const u32 dram_type;
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const u32 dram_zq;
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const u32 dram_odt_en;
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/* timing configuration */
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const u32 dram_mr0;
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const u32 dram_mr1;
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const u32 dram_mr2;
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const u32 dram_mr3;
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const u32 dram_tpr0; //DRAMTMG0
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const u32 dram_tpr1; //DRAMTMG1
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const u32 dram_tpr2; //DRAMTMG2
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const u32 dram_tpr3; //DRAMTMG3
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const u32 dram_tpr4; //DRAMTMG4
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const u32 dram_tpr5; //DRAMTMG5
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const u32 dram_tpr6; //DRAMTMG8
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const u32 dram_tpr7;
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const u32 dram_tpr8;
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const u32 dram_tpr9;
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const u32 dram_tpr10;
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const u32 dram_tpr11;
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const u32 dram_tpr12;
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} dram_para_t;
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typedef struct dram_config {
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/* control configuration */
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u32 dram_para1;
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u32 dram_para2;
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/* contains a bitfield of DRAM setup settings */
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u32 dram_tpr13;
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} dram_config_t;
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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#endif /* _SUNXI_DRAM_SUN20I_D1_H */
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