mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
095a460b49
This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. mtu.h is copied literally from the kernel sources. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/*
|
|
* (C) Copyright 2009 Alessandro Rubini
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_MTU_H
|
|
#define __ASM_ARCH_MTU_H
|
|
|
|
/*
|
|
* The MTU device hosts four different counters, with 4 set of
|
|
* registers. These are register names.
|
|
*/
|
|
|
|
#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
|
|
#define MTU_RIS 0x04 /* Raw interrupt status */
|
|
#define MTU_MIS 0x08 /* Masked interrupt status */
|
|
#define MTU_ICR 0x0C /* Interrupt clear register */
|
|
|
|
/* per-timer registers take 0..3 as argument */
|
|
#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
|
|
#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
|
|
#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
|
|
#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
|
|
|
|
/* bits for the control register */
|
|
#define MTU_CRn_ENA 0x80
|
|
#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
|
|
#define MTU_CRn_PRESCALE_MASK 0x0c
|
|
#define MTU_CRn_PRESCALE_1 0x00
|
|
#define MTU_CRn_PRESCALE_16 0x04
|
|
#define MTU_CRn_PRESCALE_256 0x08
|
|
#define MTU_CRn_32BITS 0x02
|
|
#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
|
|
|
|
/* Other registers are usual amba/primecell registers, currently not used */
|
|
#define MTU_ITCR 0xff0
|
|
#define MTU_ITOP 0xff4
|
|
|
|
#define MTU_PERIPH_ID0 0xfe0
|
|
#define MTU_PERIPH_ID1 0xfe4
|
|
#define MTU_PERIPH_ID2 0xfe8
|
|
#define MTU_PERIPH_ID3 0xfeC
|
|
|
|
#define MTU_PCELL0 0xff0
|
|
#define MTU_PCELL1 0xff4
|
|
#define MTU_PCELL2 0xff8
|
|
#define MTU_PCELL3 0xffC
|
|
|
|
#endif /* __ASM_ARCH_MTU_H */
|