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aa48c94ca8
Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
57 lines
986 B
C
57 lines
986 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#ifndef _ASM_ARCH_GPIO_H
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#define _ASM_ARCH_GPIO_H
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struct rockchip_gpio_regs {
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u32 swport_dr;
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u32 swport_ddr;
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u32 reserved0[(0x30 - 0x08) / 4];
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u32 inten;
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u32 intmask;
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u32 inttype_level;
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u32 int_polarity;
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u32 int_status;
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u32 int_rawstatus;
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u32 debounce;
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u32 porta_eoi;
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u32 ext_port;
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u32 reserved1[(0x60 - 0x54) / 4];
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u32 ls_sync;
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};
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check_member(rockchip_gpio_regs, ls_sync, 0x60);
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enum gpio_pu_pd {
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GPIO_PULL_NORMAL = 0,
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GPIO_PULL_UP,
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GPIO_PULL_DOWN,
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GPIO_PULL_REPEAT,
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};
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/* These defines are only used by spl_gpio.h */
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enum {
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/* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */
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GPIO_BANK_SHIFT = 3,
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GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT,
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GPIO_OFFSET_MASK = 0x1f,
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};
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#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset))
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enum gpio_bank_t {
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BANK_A = 0,
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BANK_B,
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BANK_C,
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BANK_D,
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};
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enum gpio_dir_t {
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GPIO_INPUT = 0,
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GPIO_OUTPUT,
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};
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#endif
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