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https://github.com/AsahiLinux/u-boot
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1767ac2d1f
Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
177 lines
4 KiB
C
177 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/stpmic1.h>
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
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#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
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#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
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/* UART4 clock enable */
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setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
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#define GPIOG_BASE 0x50008000
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/* GPIOG clock enable */
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writel(BIT(6), RCC_MP_AHB4ENSETR);
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/* GPIO configuration for EVAL board
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* => Uart4 TX = G11
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*/
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writel(0xffbfffff, GPIOG_BASE + 0x00);
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writel(0x00006000, GPIOG_BASE + 0x24);
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#else
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#error("CONFIG_DEBUG_UART_BASE: not supported value")
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#endif
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}
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#endif
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#ifdef CONFIG_PMIC_STPMIC1
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int board_ddr_power_init(enum ddr_type ddr_type)
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{
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struct udevice *dev;
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bool buck3_at_1800000v = false;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_GET_DRIVER(pmic_stpmic1), &dev);
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if (ret)
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/* No PMIC on board */
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return 0;
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switch (ddr_type) {
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case STM32MP_DDR3:
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/* VTT = Set LDO3 to sync mode */
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* VDD_DDR = Set BUCK2 to 1.35V */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_VOUT_MASK,
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STPMIC1_BUCK2_1350000V);
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if (ret < 0)
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return ret;
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/* Enable VDD_DDR = BUCK2 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VREF */
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ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VTT = LDO3 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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break;
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case STM32MP_LPDDR2:
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case STM32MP_LPDDR3:
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/*
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* configure VDD_DDR1 = LDO3
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* Set LDO3 to 1.8V
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* + bypass mode if BUCK3 = 1.8V
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* + normal mode if BUCK3 != 1.8V
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*/
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ret = pmic_reg_read(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
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if (ret < 0)
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return ret;
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if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
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buck3_at_1800000v = true;
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO3_1800000;
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if (buck3_at_1800000v)
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ret |= STPMIC1_LDO3_MODE;
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* VDD_DDR2 : Set BUCK2 to 1.2V */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_VOUT_MASK,
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STPMIC1_BUCK2_1200000V);
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if (ret < 0)
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return ret;
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/* Enable VDD_DDR1 = LDO3 */
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ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VDD_DDR2 =BUCK2 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VREF */
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ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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break;
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default:
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break;
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};
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return 0;
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}
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#endif
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