mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
165 lines
5.9 KiB
C
165 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*/
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#ifndef _DCGU_H
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#define _DCGU_H
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enum dcgu_switch {
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DCGU_SWITCH_OFF, /* Switch off */
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DCGU_SWITCH_ON /* Switch on */
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};
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enum dcgu_hw_module {
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DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */
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DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */
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DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/
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DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */
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DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */
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DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */
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DCGU_HW_MODULE_DVP, /* Selects dig video processing module */
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DCGU_HW_MODULE_CVE, /* Selects color video encoder module */
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DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */
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DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */
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DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */
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DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */
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DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */
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DCGU_HW_MODULE_UART_1, /* Selects first UART module */
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DCGU_HW_MODULE_UART_2, /* Selects second UART module */
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DCGU_HW_MODULE_AD, /* Selects audio decoder module */
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DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */
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DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
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DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */
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DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/
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DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */
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DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
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DCGU_HW_MODULE_USBH, /* Selects USB hub module */
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DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
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DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */
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DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */
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DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/
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DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/
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DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/
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DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */
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DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */
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DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */
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DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/
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DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/
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DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
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DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
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DCGU_HW_MODULE_COM, /* Selects COM unit module */
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DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
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DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */
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DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/
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DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */
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DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */
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DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */
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DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */
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DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */
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DCGU_HW_MODULE_SRAM, /* Selects SRAM module */
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DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/
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DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */
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DCGU_HW_MODULE_SCC, /* Selects SCC module */
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DCGU_HW_MODULE_MM, /* Selects Memory Manager module */
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DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */
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DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */
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DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */
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DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */
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DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/
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};
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union dcgu_clk_en1 {
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u32 reg;
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struct {
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u32 res1:8; /* reserved */
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u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
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u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
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u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
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u32 en_clksmc:1; /* Enable bit for clksmc (#) */
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u32 en_clkebi:1; /* Enable bit for clkebi (#) */
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u32 en_usbpll:1; /* Enable bit for the USB PLL */
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u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */
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u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */
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u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */
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u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */
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u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */
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u32 res2:3; /* reserved */
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u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */
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u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */
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u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */
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u32 en_clkad:1; /* Enable bit for clkad (#) */
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u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */
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u32 en_clktsd:1; /* Enable bit for clktsd (#) */
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u32 en_clkga:1; /* Enable bit for clkga (#) */
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u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */
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u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */
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u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */
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} bits;
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};
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union dcgu_clk_en2 {
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u32 reg;
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struct {
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u32 res1:31; /* reserved */
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u32 en_clkcpu:1; /* Enable bit for clkcpu */
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} bits;
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};
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union dcgu_reset_unit1 {
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u32 reg;
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struct {
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u32 res1:1;
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u32 swreset_clkmsmc:1;
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u32 swreset_clkssi_s:1;
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u32 swreset_clkssi_m:1;
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u32 swreset_clksmc:1;
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u32 swreset_clkebi:1;
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u32 swreset_clkusb60:1;
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u32 swreset_clkusb24:1;
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u32 swreset_clkuart2:1;
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u32 swreset_clkuart1:1;
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u32 swreset_pwm:1;
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u32 swreset_gpt:1;
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u32 swreset_i2c2:1;
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u32 swreset_i2c1:1;
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u32 swreset_gpio2:1;
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u32 swreset_gpio1:1;
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u32 swreset_clkcpu:1;
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u32 res2:2;
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u32 swreset_clk_i2s_dly:1;
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u32 swreset_clk_scc_abp:1;
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u32 swreset_clk_dtv_spdo:1;
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u32 swreset_clkad:1;
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u32 swreset_clkmvd:1;
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u32 swreset_clktsd:1;
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u32 swreset_clktsio:1;
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u32 swreset_clkga:1;
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u32 swreset_clkmpc:1;
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u32 swreset_clkcve:1;
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u32 swreset_clkdvp:1;
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u32 swreset_clkmr2:1;
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u32 swreset_clkmr1:1;
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} bits;
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};
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int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
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int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
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#endif /* _DCGU_H */
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