mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
392 lines
5.6 KiB
ArmAsm
392 lines
5.6 KiB
ArmAsm
/* Memory sub-system initialization code */
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/au1x00.h>
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#include <asm/mipsregs.h>
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#define AU1500_SYS_ADDR 0xB1900000
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#define sys_endian 0x0038
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#define CP0_Config0 $16
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#define MEM_1MS ((396000000/1000000) * 1000)
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.text
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.set noreorder
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.set mips32
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Step 1) Establish CPU endian mode.
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* NOTE: A fair amount of code is necessary on the Pb1000 to
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* obtain the value of Switch S8.1 which is used to determine
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* endian at run-time.
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*/
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/* RCE1 */
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li t0, MEM_STCFG1
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li t1, 0x00000083
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sw t1, 0(t0)
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li t0, MEM_STTIME1
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li t1, 0x33030A10
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sw t1, 0(t0)
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li t0, MEM_STADDR1
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li t1, 0x11803E40
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sw t1, 0(t0)
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/* Set DSTRB bits so switch will read correctly */
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li t1, 0xBE00000C
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lw t2, 0(t1)
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or t2, t2, 0x00000300
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sw t2, 0(t1)
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/* Check switch setting */
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li t1, 0xBE000014
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lw t2, 0(t1)
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and t2, t2, 0x00000100
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bne t2, zero, big_endian
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nop
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little_endian:
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/* Change Au1 core to little endian */
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li t0, AU1500_SYS_ADDR
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li t1, 1
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sw t1, sys_endian(t0)
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mfc0 t2, CP0_CONFIG
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mtc0 t2, CP0_CONFIG
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nop
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nop
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/* Big Endian is default so nothing to do but fall through */
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big_endian:
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/*
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* Step 2) Establish Status Register
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* (set BEV, clear ERL, clear EXL, clear IE)
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*/
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li t1, 0x00400000
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mtc0 t1, CP0_STATUS
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/*
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* Step 3) Establish CP0 Config0
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* (set OD, set K0=3)
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*/
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li t1, 0x00080003
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mtc0 t1, CP0_CONFIG
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/*
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* Step 4) Disable Watchpoint facilities
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*/
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li t1, 0x00000000
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mtc0 t1, CP0_WATCHLO
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mtc0 t1, CP0_IWATCHLO
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/*
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* Step 5) Disable the performance counters
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*/
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mtc0 zero, CP0_PERFORMANCE
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nop
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/*
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* Step 6) Establish EJTAG Debug register
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*/
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mtc0 zero, CP0_DEBUG
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nop
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/*
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* Step 7) Establish Cause
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* (set IV bit)
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*/
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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/* Establish Wired (and Random) */
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mtc0 zero, CP0_WIRED
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nop
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/* First setup pll:s to make serial work ok */
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/* We have a 12 MHz crystal */
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li t0, SYS_CPUPLL
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li t1, 0x21 /* 396 MHz */
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sw t1, 0(t0)
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sync
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nop
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nop
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/* wait 1mS for clocks to settle */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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/* Setup AUX PLL */
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li t0, SYS_AUXPLL
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li t1, 8 /* 96 MHz */
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sw t1, 0(t0) /* aux pll */
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sync
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/* Static memory controller */
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/* RCE0 8MB AMD29D323 Flash */
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li t0, MEM_STCFG0
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li t1, 0x00001403
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sw t1, 0(t0)
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li t0, MEM_STTIME0
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li t1, 0xFFFFFFDD
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sw t1, 0(t0)
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li t0, MEM_STADDR0
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li t1, 0x11F83FE0
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sw t1, 0(t0)
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/* RCE1 CPLD Board Logic */
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li t0, MEM_STCFG1
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li t1, 0x00000083
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sw t1, 0(t0)
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li t0, MEM_STTIME1
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li t1, 0x33030A10
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sw t1, 0(t0)
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li t0, MEM_STADDR1
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li t1, 0x11803E40
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sw t1, 0(t0)
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/* RCE2 CPLD Board Logic */
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li t0, MEM_STCFG2
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li t1, 0x00000004
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sw t1, 0(t0)
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li t0, MEM_STTIME2
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li t1, 0x08061908
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sw t1, 0(t0)
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li t0, MEM_STADDR2
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li t1, 0x12A03FC0
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sw t1, 0(t0)
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/* RCE3 PCMCIA 250ns */
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li t0, MEM_STCFG3
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li t1, 0x00000002
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sw t1, 0(t0)
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li t0, MEM_STTIME3
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li t1, 0x280E3E07
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sw t1, 0(t0)
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li t0, MEM_STADDR3
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li t1, 0x10000000
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sw t1, 0(t0)
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sync
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/* Set peripherals to a known state */
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li t0, IC0_CFG0CLR
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li t1, 0xFFFFFFFF
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sw t1, 0(t0)
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li t0, IC0_CFG0CLR
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sw t1, 0(t0)
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li t0, IC0_CFG1CLR
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sw t1, 0(t0)
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li t0, IC0_CFG2CLR
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sw t1, 0(t0)
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li t0, IC0_SRCSET
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sw t1, 0(t0)
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li t0, IC0_ASSIGNSET
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sw t1, 0(t0)
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li t0, IC0_WAKECLR
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sw t1, 0(t0)
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li t0, IC0_RISINGCLR
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sw t1, 0(t0)
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li t0, IC0_FALLINGCLR
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sw t1, 0(t0)
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li t0, IC0_TESTBIT
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, IC1_CFG0CLR
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li t1, 0xFFFFFFFF
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sw t1, 0(t0)
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li t0, IC1_CFG0CLR
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sw t1, 0(t0)
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li t0, IC1_CFG1CLR
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sw t1, 0(t0)
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li t0, IC1_CFG2CLR
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sw t1, 0(t0)
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li t0, IC1_SRCSET
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sw t1, 0(t0)
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li t0, IC1_ASSIGNSET
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sw t1, 0(t0)
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li t0, IC1_WAKECLR
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sw t1, 0(t0)
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li t0, IC1_RISINGCLR
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sw t1, 0(t0)
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li t0, IC1_FALLINGCLR
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sw t1, 0(t0)
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li t0, IC1_TESTBIT
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, SYS_FREQCTRL0
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_FREQCTRL1
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_CLKSRC
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_PININPUTEN
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li t1, 0x00000000
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sw t1, 0(t0)
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sync
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li t0, 0xB1100100
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, 0xB1400100
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_WAKEMSK
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, SYS_WAKESRC
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li t1, 0x00000000
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sw t1, 0(t0)
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/* wait 1mS before setup */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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/*
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* Skip memory setup if we are running from memory
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*/
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li t0, 0x90000000
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sub t0, ra, t0
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bltz t0, skip_memsetup
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nop
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/*
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* SDCS0 - Not used, for SMROM
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* SDCS1 - 32MB Micron 48LCBM16A2
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* SDCS2 - 32MB Micron 48LCBM16A2
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*/
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li t0, MEM_SDMODE0
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, MEM_SDMODE1
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li t1, 0x00552229
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sw t1, 0(t0)
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li t0, MEM_SDMODE2
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li t1, 0x00552229
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sw t1, 0(t0)
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li t0, MEM_SDADDR0
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li t1, 0x00000000
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sw t1, 0(t0)
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li t0, MEM_SDADDR1
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li t1, 0x001003F8
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sw t1, 0(t0)
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li t0, MEM_SDADDR2
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li t1, 0x001023F8
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sw t1, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x74000c30 /* Disable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDPRECMD
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sw zero, 0(t0)
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sync
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li t0, MEM_SDAUTOREF
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sw zero, 0(t0)
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sync
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sw zero, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x76000c30 /* Enable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD0
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li t1, 0x00000023
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD1
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li t1, 0x00000023
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD2
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li t1, 0x00000023
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sw t1, 0(t0)
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sync
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/* wait 1mS after setup */
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li t1, MEM_1MS
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1: add t1, -1
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bne t1, zero, 1b
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nop
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skip_memsetup:
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li t0, SYS_PINFUNC
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li t1, 0/*0x00008080*/
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sw t1, 0(t0)
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/*
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li t0, SYS_TRIOUTCLR
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li t1, 0x00001FFF
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sw t1, 0(t0)
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li t0, SYS_OUTPUTCLR
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li t1, 0x00008000
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sw t1, 0(t0)
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*/
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sync
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j ra
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nop
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