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The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
33 lines
1.2 KiB
Text
33 lines
1.2 KiB
Text
* Texas Instruments - dp83867 Giga bit ethernet phy
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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- enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
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compensate for the board being designed with the lanes swapped.
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- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
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TX/RX lanes.
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- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
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for applicable values
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Default child nodes are standard Ethernet PHY device
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nodes as described in doc/devicetree/bindings/net/ethernet.txt
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Example:
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ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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enet-phy-lane-no-swap;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
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};
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Datasheet can be found:
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http://www.ti.com/product/DP83867IR/datasheet
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