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The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
385 lines
8.5 KiB
C
385 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI divider clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/divider.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <asm/io.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/log2.h>
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#include "clk.h"
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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struct clk_ti_divider_priv {
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struct clk parent;
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struct clk_ti_reg reg;
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const struct clk_div_table *table;
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u8 shift;
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u8 flags;
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u8 div_flags;
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s8 latch;
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u16 min;
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u16 max;
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u16 mask;
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};
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static unsigned int _get_div(const struct clk_div_table *table, ulong flags,
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unsigned int val)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (table)
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return clk_divider_get_table_div(table, val);
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return val + 1;
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}
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static unsigned int _get_val(const struct clk_div_table *table, ulong flags,
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unsigned int div)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (table)
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return clk_divider_get_table_val(table, div);
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return div - 1;
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}
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static int _div_round_up(const struct clk_div_table *table, ulong parent_rate,
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ulong rate)
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{
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const struct clk_div_table *clkt;
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int up = INT_MAX;
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int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div < div)
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continue;
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if ((clkt->div - div) < (up - div))
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up = clkt->div;
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}
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return up;
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}
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static int _div_round(const struct clk_div_table *table, ulong parent_rate,
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ulong rate)
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{
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if (table)
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return _div_round_up(table, parent_rate, rate);
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return DIV_ROUND_UP(parent_rate, rate);
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}
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static int clk_ti_divider_best_div(struct clk *clk, ulong rate,
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ulong *best_parent_rate)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
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ulong parent_rate, parent_round_rate, max_div;
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ulong best_rate, r;
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int i, best_div = 0;
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parent_rate = clk_get_rate(&priv->parent);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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if (!rate)
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rate = 1;
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if (!(clk->flags & CLK_SET_RATE_PARENT)) {
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best_div = _div_round(priv->table, parent_rate, rate);
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if (best_div == 0)
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best_div = 1;
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if (best_div > priv->max)
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best_div = priv->max;
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*best_parent_rate = parent_rate;
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return best_div;
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}
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max_div = min(ULONG_MAX / rate, (ulong)priv->max);
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for (best_rate = 0, i = 1; i <= max_div; i++) {
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if (!clk_divider_is_valid_div(priv->table, priv->div_flags, i))
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continue;
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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if ((rate * i) == parent_rate) {
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*best_parent_rate = parent_rate;
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dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n",
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rate, rate, i);
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return i;
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}
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parent_round_rate = clk_round_rate(&priv->parent,
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MULT_ROUND_UP(rate, i));
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if (IS_ERR_VALUE(parent_round_rate))
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continue;
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r = DIV_ROUND_UP(parent_round_rate, i);
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if (r <= rate && r > best_rate) {
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best_div = i;
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best_rate = r;
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*best_parent_rate = parent_round_rate;
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if (best_rate == rate)
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break;
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}
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}
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if (best_div == 0) {
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best_div = priv->max;
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parent_round_rate = clk_round_rate(&priv->parent, 1);
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if (IS_ERR_VALUE(parent_round_rate))
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return parent_round_rate;
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}
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dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n", rate, best_rate,
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best_div);
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return best_div;
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}
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static ulong clk_ti_divider_round_rate(struct clk *clk, ulong rate)
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{
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ulong parent_rate;
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int div;
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div = clk_ti_divider_best_div(clk, rate, &parent_rate);
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if (div < 0)
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return div;
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return DIV_ROUND_UP(parent_rate, div);
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}
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static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
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ulong parent_rate;
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int div;
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u32 val, v;
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div = clk_ti_divider_best_div(clk, rate, &parent_rate);
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if (div < 0)
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return div;
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if (clk->flags & CLK_SET_RATE_PARENT) {
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parent_rate = clk_set_rate(&priv->parent, parent_rate);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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}
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val = _get_val(priv->table, priv->div_flags, div);
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v = clk_ti_readl(&priv->reg);
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v &= ~(priv->mask << priv->shift);
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v |= val << priv->shift;
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clk_ti_writel(v, &priv->reg);
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clk_ti_latch(&priv->reg, priv->latch);
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return clk_get_rate(clk);
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}
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static ulong clk_ti_divider_get_rate(struct clk *clk)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
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ulong rate, parent_rate;
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unsigned int div;
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u32 v;
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parent_rate = clk_get_rate(&priv->parent);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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v = clk_ti_readl(&priv->reg) >> priv->shift;
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v &= priv->mask;
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div = _get_div(priv->table, priv->div_flags, v);
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if (!div) {
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if (!(priv->div_flags & CLK_DIVIDER_ALLOW_ZERO))
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dev_warn(clk->dev,
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"zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n");
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return parent_rate;
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}
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rate = DIV_ROUND_UP(parent_rate, div);
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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static int clk_ti_divider_request(struct clk *clk)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
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clk->flags = priv->flags;
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return 0;
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}
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const struct clk_ops clk_ti_divider_ops = {
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.request = clk_ti_divider_request,
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.round_rate = clk_ti_divider_round_rate,
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.get_rate = clk_ti_divider_get_rate,
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.set_rate = clk_ti_divider_set_rate
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};
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static int clk_ti_divider_remove(struct udevice *dev)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(&priv->parent, 1);
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if (err) {
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dev_err(dev, "failed to release parent clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_divider_probe(struct udevice *dev)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_by_index(dev, 0, &priv->parent);
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if (err) {
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dev_err(dev, "failed to get parent clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_divider_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_divider_priv *priv = dev_get_priv(dev);
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struct clk_div_table *table = NULL;
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u32 val, valid_div;
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u32 min_div = 0;
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u32 max_val, max_div = 0;
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u16 mask;
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int i, div_num, err;
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err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
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if (err) {
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dev_err(dev, "failed to get register address\n");
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return err;
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}
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priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
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priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
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if (dev_read_bool(dev, "ti,index-starts-at-one"))
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priv->div_flags |= CLK_DIVIDER_ONE_BASED;
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if (dev_read_bool(dev, "ti,index-power-of-two"))
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priv->div_flags |= CLK_DIVIDER_POWER_OF_TWO;
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if (dev_read_bool(dev, "ti,set-rate-parent"))
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priv->flags |= CLK_SET_RATE_PARENT;
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if (dev_read_prop(dev, "ti,dividers", &div_num)) {
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div_num /= sizeof(u32);
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/* Determine required size for divider table */
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for (i = 0, valid_div = 0; i < div_num; i++) {
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dev_read_u32_index(dev, "ti,dividers", i, &val);
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if (val)
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valid_div++;
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}
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if (!valid_div) {
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dev_err(dev, "no valid dividers\n");
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return -EINVAL;
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}
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table = calloc(valid_div + 1, sizeof(*table));
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if (!table)
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return -ENOMEM;
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for (i = 0, valid_div = 0; i < div_num; i++) {
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dev_read_u32_index(dev, "ti,dividers", i, &val);
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if (!val)
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continue;
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table[valid_div].div = val;
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table[valid_div].val = i;
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valid_div++;
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if (val > max_div)
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max_div = val;
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if (!min_div || val < min_div)
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min_div = val;
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}
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max_val = max_div;
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} else {
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/* Divider table not provided, determine min/max divs */
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min_div = dev_read_u32_default(dev, "ti,min-div", 1);
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if (dev_read_u32(dev, "ti,max-div", &max_div)) {
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dev_err(dev, "missing 'max-div' property\n");
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return -EFAULT;
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}
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max_val = max_div;
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if (!(priv->div_flags & CLK_DIVIDER_ONE_BASED) &&
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!(priv->div_flags & CLK_DIVIDER_POWER_OF_TWO))
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max_val--;
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}
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priv->table = table;
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priv->min = min_div;
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priv->max = max_div;
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if (priv->div_flags & CLK_DIVIDER_POWER_OF_TWO)
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mask = fls(max_val) - 1;
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else
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mask = max_val;
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priv->mask = (1 << fls(mask)) - 1;
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return 0;
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}
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static const struct udevice_id clk_ti_divider_of_match[] = {
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{.compatible = "ti,divider-clock"},
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{}
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};
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U_BOOT_DRIVER(clk_ti_divider) = {
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.name = "ti_divider_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_divider_of_match,
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.of_to_plat = clk_ti_divider_of_to_plat,
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.probe = clk_ti_divider_probe,
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.remove = clk_ti_divider_remove,
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.priv_auto = sizeof(struct clk_ti_divider_priv),
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.ops = &clk_ti_divider_ops,
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};
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