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165e8fe5db
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Dario Binacchi <dariobin@libero.it>
413 lines
10 KiB
C
413 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI DPLL clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/dpll.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <hang.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include "clk.h"
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struct clk_ti_am3_dpll_drv_data {
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ulong max_rate;
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};
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struct clk_ti_am3_dpll_priv {
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struct clk_ti_reg clkmode_reg;
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struct clk_ti_reg idlest_reg;
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struct clk_ti_reg clksel_reg;
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struct clk_ti_reg ssc_deltam_reg;
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struct clk_ti_reg ssc_modfreq_reg;
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struct clk clk_bypass;
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struct clk clk_ref;
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u16 last_rounded_mult;
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u8 last_rounded_div;
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u8 min_div;
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ulong max_rate;
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u32 ssc_modfreq;
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u32 ssc_deltam;
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bool ssc_downspread;
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};
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static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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ulong ret, ref_rate, r;
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int m, d, err_min, err;
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int mult = INT_MAX, div = INT_MAX;
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if (priv->max_rate && rate > priv->max_rate) {
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dev_warn(clk->dev, "%ld is to high a rate, lowered to %ld\n",
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rate, priv->max_rate);
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rate = priv->max_rate;
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}
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ret = -EFAULT;
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err = rate;
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err_min = rate;
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ref_rate = clk_get_rate(&priv->clk_ref);
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for (d = priv->min_div; err_min && d <= 128; d++) {
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for (m = 2; m <= 2047; m++) {
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r = (ref_rate * m) / d;
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err = abs(r - rate);
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if (err < err_min) {
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err_min = err;
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ret = r;
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mult = m;
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div = d;
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if (err == 0)
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break;
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} else if (r > rate) {
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break;
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}
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}
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}
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priv->last_rounded_mult = mult;
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priv->last_rounded_div = div;
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dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n",
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rate, priv->min_div, ret, mult, div);
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return ret;
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}
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static void clk_ti_am3_dpll_clken(struct clk_ti_am3_dpll_priv *priv,
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u8 clken_bits)
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{
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u32 v;
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v = clk_ti_readl(&priv->clkmode_reg);
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v &= ~CM_CLKMODE_DPLL_DPLL_EN_MASK;
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v |= clken_bits << CM_CLKMODE_DPLL_EN_SHIFT;
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clk_ti_writel(v, &priv->clkmode_reg);
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}
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static int clk_ti_am3_dpll_state(struct clk *clk, u8 state)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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u32 i = 0, v;
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do {
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v = clk_ti_readl(&priv->idlest_reg) & ST_DPLL_CLK_MASK;
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if (v == state) {
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dev_dbg(clk->dev, "transition to '%s' in %d loops\n",
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state ? "locked" : "bypassed", i);
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return 1;
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}
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} while (++i < LDELAY);
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dev_err(clk->dev, "failed transition to '%s'\n",
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state ? "locked" : "bypassed");
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return 0;
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}
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/**
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* clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers
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* @clk: struct clk * of DPLL to set
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*
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* Enable the DPLL spread spectrum clocking if frequency modulation and
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* frequency spreading have been set, otherwise disable it.
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*/
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static void clk_ti_am3_dpll_ssc_program(struct clk *clk)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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unsigned long ref_rate;
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u32 v, ctrl, mod_freq_divider, exponent, mantissa;
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u32 deltam_step, deltam_ceil;
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ctrl = clk_ti_readl(&priv->clkmode_reg);
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if (priv->ssc_modfreq && priv->ssc_deltam) {
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ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK;
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if (priv->ssc_downspread)
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ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
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else
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ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
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ref_rate = clk_get_rate(&priv->clk_ref);
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mod_freq_divider =
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(ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq);
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if (priv->ssc_modfreq > (ref_rate / 70))
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dev_warn(clk->dev,
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"clock: SSC modulation frequency of DPLL %s greater than %ld\n",
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clk->dev->name, ref_rate / 70);
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exponent = 0;
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mantissa = mod_freq_divider;
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while ((mantissa > 127) && (exponent < 7)) {
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exponent++;
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mantissa /= 2;
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}
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if (mantissa > 127)
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mantissa = 127;
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v = clk_ti_readl(&priv->ssc_modfreq_reg);
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v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK);
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v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK);
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v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK);
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clk_ti_writel(v, &priv->ssc_modfreq_reg);
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dev_dbg(clk->dev,
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"mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n",
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mod_freq_divider, exponent, mantissa, v);
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deltam_step = priv->last_rounded_mult * priv->ssc_deltam;
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deltam_step /= 10;
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if (priv->ssc_downspread)
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deltam_step /= 2;
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deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
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deltam_step /= 100;
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deltam_step /= mod_freq_divider;
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if (deltam_step > 0xFFFFF)
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deltam_step = 0xFFFFF;
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deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >>
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__ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
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if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK)
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deltam_ceil++;
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if ((priv->ssc_downspread &&
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((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 ||
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priv->last_rounded_mult > 2045)) ||
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((priv->last_rounded_mult - deltam_ceil) < 20 ||
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(priv->last_rounded_mult + deltam_ceil) > 2045))
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dev_warn(clk->dev,
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"clock: SSC multiplier of DPLL %s is out of range\n",
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clk->dev->name);
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v = clk_ti_readl(&priv->ssc_deltam_reg);
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v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK);
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v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK |
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CM_SSC_DELTAM_DPLL_FRAC_MASK);
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clk_ti_writel(v, &priv->ssc_deltam_reg);
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dev_dbg(clk->dev,
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"deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n",
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deltam_step, deltam_ceil, v);
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} else {
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ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK;
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}
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clk_ti_writel(ctrl, &priv->clkmode_reg);
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}
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static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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u32 v;
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ulong round_rate;
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round_rate = clk_ti_am3_dpll_round_rate(clk, rate);
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if (IS_ERR_VALUE(round_rate))
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return round_rate;
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v = clk_ti_readl(&priv->clksel_reg);
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/* enter bypass mode */
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clk_ti_am3_dpll_clken(priv, DPLL_EN_MN_BYPASS);
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/* wait for bypass mode */
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clk_ti_am3_dpll_state(clk, 0);
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/* set M & N */
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v &= ~CM_CLKSEL_DPLL_M_MASK;
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v |= (priv->last_rounded_mult << CM_CLKSEL_DPLL_M_SHIFT) &
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CM_CLKSEL_DPLL_M_MASK;
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v &= ~CM_CLKSEL_DPLL_N_MASK;
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v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
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CM_CLKSEL_DPLL_N_MASK;
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clk_ti_writel(v, &priv->clksel_reg);
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clk_ti_am3_dpll_ssc_program(clk);
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/* lock dpll */
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clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
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/* wait till the dpll locks */
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if (!clk_ti_am3_dpll_state(clk, ST_DPLL_CLK_MASK))
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hang();
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return round_rate;
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}
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static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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u64 rate;
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u32 m, n, v;
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/* Return bypass rate if DPLL is bypassed */
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v = clk_ti_readl(&priv->clkmode_reg);
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v &= CM_CLKMODE_DPLL_EN_MASK;
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v >>= CM_CLKMODE_DPLL_EN_SHIFT;
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switch (v) {
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case DPLL_EN_MN_BYPASS:
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case DPLL_EN_LOW_POWER_BYPASS:
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case DPLL_EN_FAST_RELOCK_BYPASS:
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rate = clk_get_rate(&priv->clk_bypass);
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dev_dbg(clk->dev, "rate=%lld\n", rate);
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return rate;
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}
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v = clk_ti_readl(&priv->clksel_reg);
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m = v & CM_CLKSEL_DPLL_M_MASK;
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m >>= CM_CLKSEL_DPLL_M_SHIFT;
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n = v & CM_CLKSEL_DPLL_N_MASK;
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n >>= CM_CLKSEL_DPLL_N_SHIFT;
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rate = clk_get_rate(&priv->clk_ref) * m;
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do_div(rate, n + 1);
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dev_dbg(clk->dev, "rate=%lld\n", rate);
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return rate;
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}
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const struct clk_ops clk_ti_am3_dpll_ops = {
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.round_rate = clk_ti_am3_dpll_round_rate,
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.get_rate = clk_ti_am3_dpll_get_rate,
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.set_rate = clk_ti_am3_dpll_set_rate,
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};
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static int clk_ti_am3_dpll_remove(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(&priv->clk_bypass, 1);
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if (err) {
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dev_err(dev, "failed to release bypass clock\n");
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return err;
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}
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err = clk_release_all(&priv->clk_ref, 1);
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if (err) {
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dev_err(dev, "failed to release reference clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_probe(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_by_index(dev, 0, &priv->clk_ref);
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if (err) {
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dev_err(dev, "failed to get reference clock\n");
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return err;
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}
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err = clk_get_by_index(dev, 1, &priv->clk_bypass);
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if (err) {
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dev_err(dev, "failed to get bypass clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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struct clk_ti_am3_dpll_drv_data *data =
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(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
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u32 min_div;
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int err;
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priv->max_rate = data->max_rate;
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err = clk_ti_get_reg_addr(dev, 0, &priv->clkmode_reg);
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if (err) {
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dev_err(dev, "failed to get clkmode register address\n");
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return err;
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}
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err = clk_ti_get_reg_addr(dev, 1, &priv->idlest_reg);
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if (err) {
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dev_err(dev, "failed to get idlest register\n");
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return -EINVAL;
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}
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err = clk_ti_get_reg_addr(dev, 2, &priv->clksel_reg);
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if (err) {
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dev_err(dev, "failed to get clksel register\n");
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return err;
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}
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err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg);
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if (err) {
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dev_err(dev, "failed to get SSC deltam register\n");
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return err;
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}
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err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg);
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if (err) {
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dev_err(dev, "failed to get SSC modfreq register\n");
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return err;
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}
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if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq))
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priv->ssc_modfreq = 0;
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if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam))
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priv->ssc_deltam = 0;
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priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread");
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if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 ||
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min_div > 128)
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priv->min_div = 1;
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else
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priv->min_div = min_div;
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return 0;
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}
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static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_data = {
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.max_rate = 1000000000
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};
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static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_j_type_data = {
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.max_rate = 2000000000
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};
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static const struct clk_ti_am3_dpll_drv_data dpll_core_data = {
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.max_rate = 1000000000
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};
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static const struct udevice_id clk_ti_am3_dpll_of_match[] = {
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{.compatible = "ti,am3-dpll-core-clock",
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.data = (ulong)&dpll_core_data},
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{.compatible = "ti,am3-dpll-no-gate-clock",
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.data = (ulong)&dpll_no_gate_data},
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{.compatible = "ti,am3-dpll-no-gate-j-type-clock",
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.data = (ulong)&dpll_no_gate_j_type_data},
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{}
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};
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U_BOOT_DRIVER(clk_ti_am3_dpll) = {
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.name = "ti_am3_dpll_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_am3_dpll_of_match,
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.of_to_plat = clk_ti_am3_dpll_of_to_plat,
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.probe = clk_ti_am3_dpll_probe,
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.remove = clk_ti_am3_dpll_remove,
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.priv_auto = sizeof(struct clk_ti_am3_dpll_priv),
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.ops = &clk_ti_am3_dpll_ops,
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};
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