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https://github.com/AsahiLinux/u-boot
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b092f96290
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
201 lines
5.5 KiB
C
201 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
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#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
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#include <linux/bitops.h>
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enum clk_reg_layout {
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CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
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CLK_REG_LAYOUT_RCAR_V3U,
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};
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struct cpg_mssr_info {
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const struct cpg_core_clk *core_clk;
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unsigned int core_clk_size;
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enum clk_reg_layout reg_layout;
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const struct mssr_mod_clk *mod_clk;
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unsigned int mod_clk_size;
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const struct mstp_stop_table *mstp_table;
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unsigned int mstp_table_size;
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const char *reset_node;
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unsigned int reset_modemr_offset;
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const char *extalr_node;
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const char *extal_usb_node;
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unsigned int mod_clk_base;
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unsigned int clk_extal_id;
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unsigned int clk_extalr_id;
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unsigned int clk_extal_usb_id;
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unsigned int pll0_div;
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const void *(*get_pll_config)(const u32 cpg_mode);
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const u16 *status_regs;
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const u16 *control_regs;
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const u16 *reset_regs;
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const u16 *reset_clear_regs;
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};
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/*
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* Definitions of CPG Core Clocks
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*
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* These include:
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* - Clock outputs exported to DT
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* - External input clocks
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* - Internal CPG clocks
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*/
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struct cpg_core_clk {
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/* Common */
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const char *name;
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unsigned int id;
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unsigned int type;
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/* Depending on type */
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unsigned int parent; /* Core Clocks only */
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unsigned int div;
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unsigned int mult;
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unsigned int offset;
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};
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enum clk_types {
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/* Generic */
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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CLK_TYPE_FR, /* Fixed Rate Clock */
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/* Custom definitions start here */
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CLK_TYPE_CUSTOM,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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{ .name = _name, .id = _id, .type = _type }
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#define DEF_BASE(_name, _id, _type, _parent...) \
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DEF_TYPE(_name, _id, _type, .parent = _parent)
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#define DEF_INPUT(_name, _id) \
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DEF_TYPE(_name, _id, CLK_TYPE_IN)
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#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV6P1(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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#define DEF_RATE(_name, _id, _rate) \
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DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
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/*
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* Definitions of Module Clocks
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*/
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struct mssr_mod_clk {
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const char *name;
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unsigned int id;
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unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
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};
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/* Convert from sparse base-100 to packed index space */
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#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
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#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
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#define DEF_MOD(_name, _mod, _parent...) \
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{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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struct mstp_stop_table {
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u32 sdis;
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u32 sen;
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u32 rdis;
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u32 ren;
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};
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#define TSTR0 0x04
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#define TSTR0_STR0 BIT(0)
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bool renesas_clk_is_mod(struct clk *clk);
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr);
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core);
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent);
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int renesas_clk_endisable(struct clk *clk, void __iomem *base,
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struct cpg_mssr_info *info, bool enable);
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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static const u16 mstpsr_for_v3u[] = {
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0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
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0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
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};
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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static const u16 mstpcr_for_v3u[] = {
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0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
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0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
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};
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/*
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* Software Reset Register offsets
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*/
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static const u16 srcr[] = {
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0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
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0x920, 0x924, 0x928, 0x92C,
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};
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static const u16 srcr_for_v3u[] = {
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0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
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0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
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};
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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static const u16 srstclr[] = {
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0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
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0x960, 0x964, 0x968, 0x96C,
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};
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static const u16 srstclr_for_v3u[] = {
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0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
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0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
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};
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#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
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