mirror of
https://github.com/AsahiLinux/u-boot
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85bb3a4eee
Adjust clock to stay compatible with those used by the Linux kernel device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
1220 lines
29 KiB
C
1220 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) ASPEED Technology Inc.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <linux/delay.h>
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#include <asm/arch/scu_ast2600.h>
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#include <asm/global_data.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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#include <dt-bindings/reset/ast2600-reset.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CLKIN_25M 25000000UL
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/* MAC Clock Delay settings */
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#define MAC12_DEF_DELAY_1G 0x0028a410
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#define MAC12_DEF_DELAY_100M 0x00410410
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#define MAC12_DEF_DELAY_10M 0x00410410
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#define MAC34_DEF_DELAY_1G 0x00104208
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#define MAC34_DEF_DELAY_100M 0x00104208
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#define MAC34_DEF_DELAY_10M 0x00104208
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/*
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* 3-bit encode of CPU freqeucy
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* Some code is duplicated
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*/
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enum ast2600_cpu_freq {
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CPU_FREQ_1200M_1,
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CPU_FREQ_1600M_1,
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CPU_FREQ_1200M_2,
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CPU_FREQ_1600M_2,
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CPU_FREQ_800M_1,
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CPU_FREQ_800M_2,
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CPU_FREQ_800M_3,
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CPU_FREQ_800M_4,
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};
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struct ast2600_clk_priv {
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struct ast2600_scu *scu;
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};
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/*
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* Clock divider/multiplier configuration struct.
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* For H-PLL and M-PLL the formula is
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* (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
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* M - Numerator
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* N - Denumerator
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* P - Post Divider
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* They have the same layout in their control register.
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*
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* D-PLL and D2-PLL have extra divider (OD + 1), which is not
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* yet needed and ignored by clock configurations.
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*/
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union ast2600_pll_reg {
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uint32_t w;
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struct {
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unsigned int m : 13;
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unsigned int n : 6;
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unsigned int p : 4;
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unsigned int off : 1;
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unsigned int bypass : 1;
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unsigned int reset : 1;
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unsigned int reserved : 6;
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} b;
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};
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struct ast2600_pll_cfg {
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union ast2600_pll_reg reg;
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unsigned int ext_reg;
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};
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struct ast2600_pll_desc {
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uint32_t in;
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uint32_t out;
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struct ast2600_pll_cfg cfg;
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};
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static const struct ast2600_pll_desc ast2600_pll_lookup[] = {
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{
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.in = CLKIN_25M,
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.out = 400000000,
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.cfg.reg.b.m = 95,
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.cfg.reg.b.n = 2,
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.cfg.reg.b.p = 1,
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.cfg.ext_reg = 0x31,
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},
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{
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.in = CLKIN_25M,
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.out = 200000000,
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.cfg.reg.b.m = 127,
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.cfg.reg.b.n = 0,
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.cfg.reg.b.p = 15,
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.cfg.ext_reg = 0x3f,
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},
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{
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.in = CLKIN_25M,
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.out = 334000000,
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.cfg.reg.b.m = 667,
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.cfg.reg.b.n = 4,
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.cfg.reg.b.p = 9,
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.cfg.ext_reg = 0x14d,
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},
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{
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.in = CLKIN_25M,
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.out = 1000000000,
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.cfg.reg.b.m = 119,
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.cfg.reg.b.n = 2,
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.cfg.reg.b.p = 0,
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.cfg.ext_reg = 0x3d,
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},
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{
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.in = CLKIN_25M,
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.out = 50000000,
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.cfg.reg.b.m = 95,
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.cfg.reg.b.n = 2,
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.cfg.reg.b.p = 15,
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.cfg.ext_reg = 0x31,
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},
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};
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/* divisor tables */
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static uint32_t axi_ahb_div0_table[] = {
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3, 2, 3, 4,
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};
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static uint32_t axi_ahb_div1_table[] = {
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3, 4, 6, 8,
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};
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static uint32_t axi_ahb_default_table[] = {
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3, 4, 3, 4, 2, 2, 2, 2,
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};
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extern uint32_t ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx)
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{
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union ast2600_pll_reg pll_reg;
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uint32_t hwstrap1;
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uint32_t cpu_freq;
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uint32_t mul = 1, div = 1;
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switch (pll_idx) {
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case ASPEED_CLK_APLL:
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pll_reg.w = readl(&scu->apll);
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break;
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case ASPEED_CLK_DPLL:
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pll_reg.w = readl(&scu->dpll);
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break;
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case ASPEED_CLK_EPLL:
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pll_reg.w = readl(&scu->epll);
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break;
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case ASPEED_CLK_HPLL:
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pll_reg.w = readl(&scu->hpll);
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break;
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case ASPEED_CLK_MPLL:
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pll_reg.w = readl(&scu->mpll);
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break;
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}
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if (!pll_reg.b.bypass) {
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/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)
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* HPLL Numerator (M) = fix 0x5F when SCU500[10]=1
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* Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1
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* SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0
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* HPLL Denumerator (N) = SCU200[18:13] (default 0x2)
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* HPLL Divider (P) = SCU200[22:19] (default 0x0)
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* HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1
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* Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1
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* SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0
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*/
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if (pll_idx == ASPEED_CLK_HPLL) {
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hwstrap1 = readl(&scu->hwstrap1);
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cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >>
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SCU_HWSTRAP1_CPU_FREQ_SHIFT;
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switch (cpu_freq) {
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case CPU_FREQ_800M_1:
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case CPU_FREQ_800M_2:
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case CPU_FREQ_800M_3:
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case CPU_FREQ_800M_4:
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pll_reg.b.m = 0x5f;
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break;
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case CPU_FREQ_1600M_1:
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case CPU_FREQ_1600M_2:
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pll_reg.b.m = 0xbf;
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break;
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default:
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pll_reg.b.m = 0x8f;
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break;
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}
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}
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mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1);
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div = (pll_reg.b.p + 1);
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}
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return ((CLKIN_25M * mul) / div);
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}
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static uint32_t ast2600_get_hclk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
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uint32_t axi_div, ahb_div;
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uint32_t hwstrap1 = readl(&scu->hwstrap1);
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uint32_t cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >>
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SCU_HWSTRAP1_CPU_FREQ_SHIFT;
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uint32_t axi_ahb_ratio = (hwstrap1 & SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK) >>
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SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT;
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if (hwstrap1 & SCU_HWSTRAP1_CPU_AXI_CLK_RATIO) {
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axi_ahb_div1_table[0] = axi_ahb_default_table[cpu_freq] * 2;
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axi_div = 1;
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ahb_div = axi_ahb_div1_table[axi_ahb_ratio];
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} else {
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axi_ahb_div0_table[0] = axi_ahb_default_table[cpu_freq];
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axi_div = 2;
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ahb_div = axi_ahb_div0_table[axi_ahb_ratio];
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}
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return (rate / axi_div / ahb_div);
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}
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static uint32_t ast2600_get_bclk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
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uint32_t clksrc1 = readl(&scu->clksrc1);
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uint32_t bclk_div = (clksrc1 & SCU_CLKSRC1_BCLK_DIV_MASK) >>
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SCU_CLKSRC1_BCLK_DIV_SHIFT;
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return (rate / ((bclk_div + 1) * 4));
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}
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static uint32_t ast2600_get_pclk1_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
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uint32_t clksrc1 = readl(&scu->clksrc1);
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uint32_t pclk_div = (clksrc1 & SCU_CLKSRC1_PCLK_DIV_MASK) >>
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SCU_CLKSRC1_PCLK_DIV_SHIFT;
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return (rate / ((pclk_div + 1) * 4));
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}
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static uint32_t ast2600_get_pclk2_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_hclk_rate(scu);
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uint32_t clksrc4 = readl(&scu->clksrc4);
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uint32_t pclk_div = (clksrc4 & SCU_CLKSRC4_PCLK_DIV_MASK) >>
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SCU_CLKSRC4_PCLK_DIV_SHIFT;
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return (rate / ((pclk_div + 1) * 2));
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}
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static uint32_t ast2600_get_uxclk_in_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = 0;
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uint32_t clksrc5 = readl(&scu->clksrc5);
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uint32_t uxclk = (clksrc5 & SCU_CLKSRC5_UXCLK_MASK) >>
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SCU_CLKSRC5_UXCLK_SHIFT;
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switch (uxclk) {
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case 0:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4;
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break;
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case 1:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2;
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break;
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case 2:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
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break;
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case 3:
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rate = ast2600_get_hclk_rate(scu);
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break;
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}
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return rate;
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}
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static uint32_t ast2600_get_huxclk_in_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = 0;
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uint32_t clksrc5 = readl(&scu->clksrc5);
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uint32_t huxclk = (clksrc5 & SCU_CLKSRC5_HUXCLK_MASK) >>
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SCU_CLKSRC5_HUXCLK_SHIFT;
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switch (huxclk) {
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case 0:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4;
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break;
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case 1:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2;
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break;
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case 2:
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
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break;
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case 3:
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rate = ast2600_get_hclk_rate(scu);
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break;
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}
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return rate;
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}
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static uint32_t ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_uxclk_in_rate(scu);
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uint32_t uart_clkgen = readl(&scu->uart_clkgen);
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uint32_t n = (uart_clkgen & SCU_UART_CLKGEN_N_MASK) >>
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SCU_UART_CLKGEN_N_SHIFT;
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uint32_t r = (uart_clkgen & SCU_UART_CLKGEN_R_MASK) >>
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SCU_UART_CLKGEN_R_SHIFT;
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return ((rate * r) / (n * 2));
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}
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static uint32_t ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_huxclk_in_rate(scu);
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uint32_t huart_clkgen = readl(&scu->huart_clkgen);
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uint32_t n = (huart_clkgen & SCU_HUART_CLKGEN_N_MASK) >>
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SCU_HUART_CLKGEN_N_SHIFT;
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uint32_t r = (huart_clkgen & SCU_HUART_CLKGEN_R_MASK) >>
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SCU_HUART_CLKGEN_R_SHIFT;
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return ((rate * r) / (n * 2));
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}
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static uint32_t ast2600_get_sdio_clk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = 0;
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uint32_t clksrc4 = readl(&scu->clksrc4);
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uint32_t sdio_div = (clksrc4 & SCU_CLKSRC4_SDIO_DIV_MASK) >>
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SCU_CLKSRC4_SDIO_DIV_SHIFT;
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if (clksrc4 & SCU_CLKSRC4_SDIO)
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
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else
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rate = ast2600_get_hclk_rate(scu);
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return (rate / ((sdio_div + 1) * 2));
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}
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static uint32_t ast2600_get_emmc_clk_rate(struct ast2600_scu *scu)
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{
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uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
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uint32_t clksrc1 = readl(&scu->clksrc1);
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uint32_t emmc_div = (clksrc1 & SCU_CLKSRC1_EMMC_DIV_MASK) >>
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SCU_CLKSRC1_EMMC_DIV_SHIFT;
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return (rate / ((emmc_div + 1) * 4));
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}
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static uint32_t ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx)
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{
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uint32_t rate = 0;
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uint32_t uart5_clk = 0;
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uint32_t clksrc2 = readl(&scu->clksrc2);
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uint32_t clksrc4 = readl(&scu->clksrc4);
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uint32_t clksrc5 = readl(&scu->clksrc5);
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uint32_t misc_ctrl1 = readl(&scu->misc_ctrl1);
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switch (uart_idx) {
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case 1:
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case 2:
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case 3:
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case 4:
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case 6:
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if (clksrc4 & BIT(uart_idx - 1))
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rate = ast2600_get_uart_huxclk_rate(scu);
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else
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rate = ast2600_get_uart_uxclk_rate(scu);
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break;
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case 5:
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/*
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* SCU0C[12] and SCU304[14] together decide
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* the UART5 clock generation
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*/
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if (misc_ctrl1 & SCU_MISC_CTRL1_UART5_DIV)
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uart5_clk = 0x1 << 1;
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if (clksrc2 & SCU_CLKSRC2_UART5)
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uart5_clk |= 0x1;
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switch (uart5_clk) {
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case 0:
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rate = 24000000;
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break;
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case 1:
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rate = 192000000;
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break;
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case 2:
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rate = 24000000 / 13;
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break;
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case 3:
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rate = 192000000 / 13;
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break;
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}
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break;
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case 7:
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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case 13:
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if (clksrc5 & BIT(uart_idx - 1))
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rate = ast2600_get_uart_huxclk_rate(scu);
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else
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rate = ast2600_get_uart_uxclk_rate(scu);
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break;
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}
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return rate;
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}
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static ulong ast2600_clk_get_rate(struct clk *clk)
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{
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struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
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ulong rate = 0;
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switch (clk->id) {
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case ASPEED_CLK_HPLL:
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case ASPEED_CLK_EPLL:
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case ASPEED_CLK_DPLL:
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case ASPEED_CLK_MPLL:
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case ASPEED_CLK_APLL:
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rate = ast2600_get_pll_rate(priv->scu, clk->id);
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break;
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case ASPEED_CLK_AHB:
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rate = ast2600_get_hclk_rate(priv->scu);
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break;
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case ASPEED_CLK_APB1:
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rate = ast2600_get_pclk1_rate(priv->scu);
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break;
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case ASPEED_CLK_APB2:
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rate = ast2600_get_pclk2_rate(priv->scu);
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break;
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case ASPEED_CLK_GATE_UART1CLK:
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rate = ast2600_get_uart_clk_rate(priv->scu, 1);
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break;
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case ASPEED_CLK_GATE_UART2CLK:
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rate = ast2600_get_uart_clk_rate(priv->scu, 2);
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break;
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case ASPEED_CLK_GATE_UART3CLK:
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rate = ast2600_get_uart_clk_rate(priv->scu, 3);
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break;
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case ASPEED_CLK_GATE_UART4CLK:
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rate = ast2600_get_uart_clk_rate(priv->scu, 4);
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break;
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case ASPEED_CLK_GATE_UART5CLK:
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rate = ast2600_get_uart_clk_rate(priv->scu, 5);
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break;
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case ASPEED_CLK_BCLK:
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rate = ast2600_get_bclk_rate(priv->scu);
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break;
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case ASPEED_CLK_SDIO:
|
|
rate = ast2600_get_sdio_clk_rate(priv->scu);
|
|
break;
|
|
case ASPEED_CLK_EMMC:
|
|
rate = ast2600_get_emmc_clk_rate(priv->scu);
|
|
break;
|
|
case ASPEED_CLK_UARTX:
|
|
rate = ast2600_get_uart_uxclk_rate(priv->scu);
|
|
break;
|
|
case ASPEED_CLK_HUARTX:
|
|
rate = ast2600_get_uart_huxclk_rate(priv->scu);
|
|
break;
|
|
default:
|
|
debug("%s: unknown clk %ld\n", __func__, clk->id);
|
|
return -ENOENT;
|
|
}
|
|
|
|
return rate;
|
|
}
|
|
|
|
/**
|
|
* @brief lookup PLL divider config by input/output rate
|
|
* @param[in] *pll - PLL descriptor
|
|
* Return: true - if PLL divider config is found, false - else
|
|
* The function caller shall fill "pll->in" and "pll->out",
|
|
* then this function will search the lookup table
|
|
* to find a valid PLL divider configuration.
|
|
*/
|
|
static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll)
|
|
{
|
|
uint32_t i;
|
|
const struct ast2600_pll_desc *def_desc;
|
|
bool is_found = false;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) {
|
|
def_desc = &ast2600_pll_lookup[i];
|
|
|
|
if (def_desc->in == pll->in && def_desc->out == pll->out) {
|
|
is_found = true;
|
|
pll->cfg.reg.w = def_desc->cfg.reg.w;
|
|
pll->cfg.ext_reg = def_desc->cfg.ext_reg;
|
|
break;
|
|
}
|
|
}
|
|
return is_found;
|
|
}
|
|
|
|
static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
|
|
struct ast2600_pll_cfg *p_cfg, int pll_idx)
|
|
{
|
|
uint32_t addr, addr_ext;
|
|
uint32_t reg;
|
|
|
|
switch (pll_idx) {
|
|
case ASPEED_CLK_HPLL:
|
|
addr = (uint32_t)(&scu->hpll);
|
|
addr_ext = (uint32_t)(&scu->hpll_ext);
|
|
break;
|
|
case ASPEED_CLK_MPLL:
|
|
addr = (uint32_t)(&scu->mpll);
|
|
addr_ext = (uint32_t)(&scu->mpll_ext);
|
|
break;
|
|
case ASPEED_CLK_DPLL:
|
|
addr = (uint32_t)(&scu->dpll);
|
|
addr_ext = (uint32_t)(&scu->dpll_ext);
|
|
break;
|
|
case ASPEED_CLK_EPLL:
|
|
addr = (uint32_t)(&scu->epll);
|
|
addr_ext = (uint32_t)(&scu->epll_ext);
|
|
break;
|
|
case ASPEED_CLK_APLL:
|
|
addr = (uint32_t)(&scu->apll);
|
|
addr_ext = (uint32_t)(&scu->apll_ext);
|
|
break;
|
|
default:
|
|
debug("unknown PLL index\n");
|
|
return 1;
|
|
}
|
|
|
|
p_cfg->reg.b.bypass = 0;
|
|
p_cfg->reg.b.off = 1;
|
|
p_cfg->reg.b.reset = 1;
|
|
|
|
reg = readl(addr);
|
|
reg &= ~GENMASK(25, 0);
|
|
reg |= p_cfg->reg.w;
|
|
writel(reg, addr);
|
|
|
|
/* write extend parameter */
|
|
writel(p_cfg->ext_reg, addr_ext);
|
|
udelay(100);
|
|
p_cfg->reg.b.off = 0;
|
|
p_cfg->reg.b.reset = 0;
|
|
reg &= ~GENMASK(25, 0);
|
|
reg |= p_cfg->reg.w;
|
|
writel(reg, addr);
|
|
while (!(readl(addr_ext) & BIT(31)))
|
|
;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)
|
|
{
|
|
struct ast2600_pll_desc mpll;
|
|
|
|
mpll.in = CLKIN_25M;
|
|
mpll.out = rate;
|
|
if (ast2600_search_clock_config(&mpll) == false) {
|
|
printf("error!! unable to find valid DDR clock setting\n");
|
|
return 0;
|
|
}
|
|
ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL);
|
|
|
|
return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
|
|
}
|
|
|
|
static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong new_rate;
|
|
|
|
switch (clk->id) {
|
|
case ASPEED_CLK_MPLL:
|
|
new_rate = ast2600_configure_ddr(priv->scu, rate);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static uint32_t ast2600_configure_mac12_clk(struct ast2600_scu *scu)
|
|
{
|
|
/* scu340[25:0]: 1G default delay */
|
|
clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0),
|
|
MAC12_DEF_DELAY_1G);
|
|
|
|
/* set 100M/10M default delay */
|
|
writel(MAC12_DEF_DELAY_100M, &scu->mac12_clk_delay_100M);
|
|
writel(MAC12_DEF_DELAY_10M, &scu->mac12_clk_delay_10M);
|
|
|
|
/* MAC AHB = HPLL / 6 */
|
|
clrsetbits_le32(&scu->clksrc1, SCU_CLKSRC1_MAC_DIV_MASK,
|
|
(0x2 << SCU_CLKSRC1_MAC_DIV_SHIFT));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t ast2600_configure_mac34_clk(struct ast2600_scu *scu)
|
|
{
|
|
/*
|
|
* scu350[31] RGMII 125M source: 0 = from IO pin
|
|
* scu350[25:0] MAC 1G delay
|
|
*/
|
|
clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)),
|
|
MAC34_DEF_DELAY_1G);
|
|
writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M);
|
|
writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M);
|
|
|
|
/*
|
|
* clock source seletion and divider
|
|
* scu310[26:24] : MAC AHB bus clock = HCLK / 2
|
|
* scu310[18:16] : RMII 50M = HCLK_200M / 4
|
|
*/
|
|
clrsetbits_le32(&scu->clksrc4,
|
|
(SCU_CLKSRC4_MAC_DIV_MASK | SCU_CLKSRC4_RMII34_DIV_MASK),
|
|
((0x0 << SCU_CLKSRC4_MAC_DIV_SHIFT)
|
|
| (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT)));
|
|
|
|
/*
|
|
* set driving strength
|
|
* scu458[3:2] : MAC4 driving strength
|
|
* scu458[1:0] : MAC3 driving strength
|
|
*/
|
|
clrsetbits_le32(&scu->pinmux16,
|
|
SCU_PINCTRL16_MAC4_DRIVING_MASK | SCU_PINCTRL16_MAC3_DRIVING_MASK,
|
|
(0x3 << SCU_PINCTRL16_MAC4_DRIVING_SHIFT)
|
|
| (0x3 << SCU_PINCTRL16_MAC3_DRIVING_SHIFT));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ast2600 RGMII clock source tree
|
|
* 125M from external PAD -------->|\
|
|
* HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2
|
|
* | |---->| divider |---->|/ +
|
|
* EPLL -->|/ |
|
|
* |
|
|
* +---------<-----------|RGMIICK PAD output enable|<-------------+
|
|
* |
|
|
* +--------------------------->|\
|
|
* | |----> RGMII 125M for MAC#3 & MAC#4
|
|
* HCLK 200M ---->|divider|---->|/
|
|
* To simplify the control flow:
|
|
* 1. RGMII 1/2 always use EPLL as the internal clock source
|
|
* 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source
|
|
* 125M from external PAD -------->|\
|
|
* | |---->RGMII 125M for MAC#1 & MAC#2
|
|
* EPLL---->| divider |--->|/ +
|
|
* |
|
|
* +<--------------------|RGMIICK PAD output enable|<-------------+
|
|
* |
|
|
* +--------------------------->RGMII 125M for MAC#3 & MAC#4
|
|
*/
|
|
#define RGMIICK_SRC_PAD 0
|
|
#define RGMIICK_SRC_EPLL 1 /* recommended */
|
|
#define RGMIICK_SRC_HPLL 2
|
|
|
|
#define RGMIICK_DIV2 1
|
|
#define RGMIICK_DIV3 2
|
|
#define RGMIICK_DIV4 3
|
|
#define RGMIICK_DIV5 4
|
|
#define RGMIICK_DIV6 5
|
|
#define RGMIICK_DIV7 6
|
|
#define RGMIICK_DIV8 7 /* recommended */
|
|
|
|
#define RMIICK_DIV4 0
|
|
#define RMIICK_DIV8 1
|
|
#define RMIICK_DIV12 2
|
|
#define RMIICK_DIV16 3
|
|
#define RMIICK_DIV20 4 /* recommended */
|
|
#define RMIICK_DIV24 5
|
|
#define RMIICK_DIV28 6
|
|
#define RMIICK_DIV32 7
|
|
|
|
struct ast2600_mac_clk_div {
|
|
uint32_t src; /* 0=external PAD, 1=internal PLL */
|
|
uint32_t fin; /* divider input speed */
|
|
uint32_t n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */
|
|
uint32_t fout; /* fout = fin / n */
|
|
};
|
|
|
|
struct ast2600_mac_clk_div rgmii_clk_defconfig = {
|
|
.src = ASPEED_CLK_EPLL,
|
|
.fin = 1000000000,
|
|
.n = RGMIICK_DIV8,
|
|
.fout = 125000000,
|
|
};
|
|
|
|
struct ast2600_mac_clk_div rmii_clk_defconfig = {
|
|
.src = ASPEED_CLK_EPLL,
|
|
.fin = 1000000000,
|
|
.n = RMIICK_DIV20,
|
|
.fout = 50000000,
|
|
};
|
|
|
|
static void ast2600_init_mac_pll(struct ast2600_scu *p_scu,
|
|
struct ast2600_mac_clk_div *p_cfg)
|
|
{
|
|
struct ast2600_pll_desc pll;
|
|
|
|
pll.in = CLKIN_25M;
|
|
pll.out = p_cfg->fin;
|
|
if (ast2600_search_clock_config(&pll) == false) {
|
|
pr_err("unable to find valid ETHNET MAC clock setting\n");
|
|
return;
|
|
}
|
|
ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src);
|
|
}
|
|
|
|
static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu,
|
|
struct ast2600_mac_clk_div *p_cfg)
|
|
{
|
|
uint32_t reg_304 = readl(&p_scu->clksrc2);
|
|
uint32_t reg_340 = readl(&p_scu->mac12_clk_delay);
|
|
uint32_t reg_350 = readl(&p_scu->mac34_clk_delay);
|
|
|
|
reg_340 &= ~GENMASK(31, 29);
|
|
/* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */
|
|
reg_340 |= BIT(28);
|
|
if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
|
|
/*
|
|
* re-init PLL if the current PLL output frequency doesn't match
|
|
* the divider setting
|
|
*/
|
|
if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
|
|
ast2600_init_mac_pll(p_scu, p_cfg);
|
|
/* scu340[31]: select RGMII 125M from internal source */
|
|
reg_340 |= BIT(31);
|
|
}
|
|
|
|
reg_304 &= ~GENMASK(23, 20);
|
|
|
|
/* set clock divider */
|
|
reg_304 |= (p_cfg->n & 0x7) << 20;
|
|
|
|
/* select internal clock source */
|
|
if (p_cfg->src == ASPEED_CLK_HPLL)
|
|
reg_304 |= BIT(23);
|
|
|
|
/* RGMII 3/4 clock source select */
|
|
reg_350 &= ~BIT(31);
|
|
|
|
writel(reg_304, &p_scu->clksrc2);
|
|
writel(reg_340, &p_scu->mac12_clk_delay);
|
|
writel(reg_350, &p_scu->mac34_clk_delay);
|
|
}
|
|
|
|
/**
|
|
* ast2600 RMII/NCSI clock source tree
|
|
* HPLL -->|\
|
|
* | |---->| divider |----> RMII 50M for MAC#1 & MAC#2
|
|
* EPLL -->|/
|
|
* HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4
|
|
*/
|
|
static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu,
|
|
struct ast2600_mac_clk_div *p_cfg)
|
|
{
|
|
uint32_t clksrc2 = readl(&p_scu->clksrc2);
|
|
uint32_t clksrc4 = readl(&p_scu->clksrc4);
|
|
|
|
if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
|
|
/*
|
|
* re-init PLL if the current PLL output frequency doesn't match
|
|
* the divider setting
|
|
*/
|
|
if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
|
|
ast2600_init_mac_pll(p_scu, p_cfg);
|
|
}
|
|
|
|
clksrc2 &= ~(SCU_CLKSRC2_RMII12 | SCU_CLKSRC2_RMII12_DIV_MASK);
|
|
|
|
/* set RMII 1/2 clock divider */
|
|
clksrc2 |= (p_cfg->n & 0x7) << 16;
|
|
|
|
/* RMII clock source selection */
|
|
if (p_cfg->src == ASPEED_CLK_HPLL)
|
|
clksrc2 |= SCU_CLKSRC2_RMII12;
|
|
|
|
/* set RMII 3/4 clock divider */
|
|
clksrc4 &= ~SCU_CLKSRC4_RMII34_DIV_MASK;
|
|
clksrc4 |= (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT);
|
|
|
|
writel(clksrc2, &p_scu->clksrc2);
|
|
writel(clksrc4, &p_scu->clksrc4);
|
|
}
|
|
|
|
static uint32_t ast2600_configure_mac(struct ast2600_scu *scu, int index)
|
|
{
|
|
uint32_t reset_bit;
|
|
uint32_t clkgate_bit;
|
|
|
|
switch (index) {
|
|
case 1:
|
|
reset_bit = BIT(ASPEED_RESET_MAC1);
|
|
clkgate_bit = SCU_CLKGATE1_MAC1;
|
|
writel(reset_bit, &scu->modrst_ctrl1);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr1);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr1);
|
|
break;
|
|
case 2:
|
|
reset_bit = BIT(ASPEED_RESET_MAC2);
|
|
clkgate_bit = SCU_CLKGATE1_MAC2;
|
|
writel(reset_bit, &scu->modrst_ctrl1);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr1);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr1);
|
|
break;
|
|
case 3:
|
|
reset_bit = BIT(ASPEED_RESET_MAC3 - 32);
|
|
clkgate_bit = SCU_CLKGATE2_MAC3;
|
|
writel(reset_bit, &scu->modrst_ctrl2);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr2);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr2);
|
|
break;
|
|
case 4:
|
|
reset_bit = BIT(ASPEED_RESET_MAC4 - 32);
|
|
clkgate_bit = SCU_CLKGATE2_MAC4;
|
|
writel(reset_bit, &scu->modrst_ctrl2);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr2);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr2);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu)
|
|
{
|
|
uint32_t clksrc1 = readl(&scu->clksrc1);
|
|
|
|
/* Configure RSA clock = HPLL/3 */
|
|
clksrc1 |= SCU_CLKSRC1_ECC_RSA;
|
|
clksrc1 &= ~SCU_CLKSRC1_ECC_RSA_DIV_MASK;
|
|
clksrc1 |= (2 << SCU_CLKSRC1_ECC_RSA_DIV_SHIFT);
|
|
|
|
writel(clksrc1, &scu->clksrc1);
|
|
}
|
|
|
|
static ulong ast2600_enable_sdclk(struct ast2600_scu *scu)
|
|
{
|
|
uint32_t reset_bit;
|
|
uint32_t clkgate_bit;
|
|
|
|
reset_bit = BIT(ASPEED_RESET_SD - 32);
|
|
clkgate_bit = SCU_CLKGATE2_SDIO;
|
|
|
|
writel(reset_bit, &scu->modrst_ctrl2);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr2);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr2);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu)
|
|
{
|
|
int i = 0;
|
|
uint32_t div = 0;
|
|
uint32_t rate = 0;
|
|
uint32_t clksrc4 = readl(&scu->clksrc4);
|
|
|
|
/*
|
|
* ast2600 SD controller max clk is 200Mhz
|
|
* use apll for clock source 800/4 = 200
|
|
* controller max is 200mhz
|
|
*/
|
|
rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
|
|
for (i = 0; i < 8; i++) {
|
|
div = (i + 1) * 2;
|
|
if ((rate / div) <= 200000000)
|
|
break;
|
|
}
|
|
clksrc4 &= ~SCU_CLKSRC4_SDIO_DIV_MASK;
|
|
clksrc4 |= (i << SCU_CLKSRC4_SDIO_DIV_SHIFT);
|
|
clksrc4 |= SCU_CLKSRC4_SDIO;
|
|
writel(clksrc4, &scu->clksrc4);
|
|
|
|
setbits_le32(&scu->clksrc4, SCU_CLKSRC4_SDIO_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu)
|
|
{
|
|
uint32_t reset_bit;
|
|
uint32_t clkgate_bit;
|
|
|
|
reset_bit = BIT(ASPEED_RESET_EMMC);
|
|
clkgate_bit = SCU_CLKGATE1_EMMC;
|
|
|
|
writel(reset_bit, &scu->modrst_ctrl1);
|
|
udelay(100);
|
|
writel(clkgate_bit, &scu->clkgate_clr1);
|
|
mdelay(10);
|
|
writel(reset_bit, &scu->modrst_clr1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu)
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{
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int i = 0;
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uint32_t div = 0;
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uint32_t rate = 0;
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uint32_t clksrc1 = readl(&scu->clksrc1);
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/*
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* ast2600 eMMC controller max clk is 200Mhz
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* HPll->1/2->|\
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* |->SCU300[11]->SCU300[14:12][1/N] +
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* MPLL------>|/ |
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* +----------------------------------------------+
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* |
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* +---------> EMMC12C[15:8][1/N]-> eMMC clk
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*/
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rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
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for (i = 0; i < 8; i++) {
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div = (i + 1) * 2;
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if ((rate / div) <= 200000000)
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break;
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}
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clksrc1 &= ~SCU_CLKSRC1_EMMC_DIV_MASK;
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clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT);
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clksrc1 |= SCU_CLKSRC1_EMMC;
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writel(clksrc1, &scu->clksrc1);
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setbits_le32(&scu->clksrc1, SCU_CLKSRC1_EMMC_EN);
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return 0;
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}
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static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu)
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{
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uint32_t reset_bit;
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uint32_t clkgate_bit;
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reset_bit = BIT(ASPEED_RESET_FSI % 32);
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clkgate_bit = SCU_CLKGATE2_FSI;
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/* The FSI clock is shared between masters. If it's already on
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* don't touch it, as that will reset the existing master.
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*/
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if (!(readl(&scu->clkgate_ctrl2) & clkgate_bit)) {
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debug("%s: already running, not touching it\n", __func__);
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return 0;
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}
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writel(reset_bit, &scu->modrst_ctrl2);
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udelay(100);
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writel(clkgate_bit, &scu->clkgate_clr2);
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mdelay(10);
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writel(reset_bit, &scu->modrst_clr2);
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return 0;
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}
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static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu)
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{
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uint32_t reset_bit;
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uint32_t clkgate_bit;
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reset_bit = BIT(ASPEED_RESET_EHCI_P1);
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clkgate_bit = SCU_CLKGATE1_USB_HUB;
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writel(reset_bit, &scu->modrst_ctrl1);
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udelay(100);
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writel(clkgate_bit, &scu->clkgate_ctrl1);
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mdelay(20);
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writel(reset_bit, &scu->modrst_clr1);
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return 0;
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}
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static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
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{
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uint32_t reset_bit;
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uint32_t clkgate_bit;
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reset_bit = BIT(ASPEED_RESET_EHCI_P2);
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clkgate_bit = SCU_CLKGATE1_USB_HOST2;
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writel(reset_bit, &scu->modrst_ctrl1);
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udelay(100);
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writel(clkgate_bit, &scu->clkgate_clr1);
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mdelay(20);
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writel(reset_bit, &scu->modrst_clr1);
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return 0;
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}
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static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
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{
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uint32_t reset_bit;
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uint32_t clkgate_bit;
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/* share the same reset control bit with ACRY */
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reset_bit = BIT(ASPEED_RESET_HACE);
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clkgate_bit = SCU_CLKGATE1_HACE;
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/*
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* we don't do reset assertion here as HACE
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* shares the same reset control with ACRY
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*/
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writel(clkgate_bit, &scu->clkgate_clr1);
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mdelay(20);
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writel(reset_bit, &scu->modrst_clr1);
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return 0;
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}
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static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
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{
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uint32_t reset_bit;
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uint32_t clkgate_bit;
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/* same reset control bit with HACE */
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reset_bit = BIT(ASPEED_RESET_HACE);
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clkgate_bit = SCU_CLKGATE1_ACRY;
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/*
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* we don't do reset assertion here as HACE
|
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* shares the same reset control with ACRY
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*/
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writel(clkgate_bit, &scu->clkgate_clr1);
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mdelay(20);
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writel(reset_bit, &scu->modrst_clr1);
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return 0;
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}
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|
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static int ast2600_clk_enable(struct clk *clk)
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{
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struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
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|
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switch (clk->id) {
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case ASPEED_CLK_GATE_MAC1CLK:
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ast2600_configure_mac(priv->scu, 1);
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break;
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case ASPEED_CLK_GATE_MAC2CLK:
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ast2600_configure_mac(priv->scu, 2);
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break;
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case ASPEED_CLK_GATE_MAC3CLK:
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ast2600_configure_mac(priv->scu, 3);
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break;
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case ASPEED_CLK_GATE_MAC4CLK:
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ast2600_configure_mac(priv->scu, 4);
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break;
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case ASPEED_CLK_GATE_SDCLK:
|
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ast2600_enable_sdclk(priv->scu);
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break;
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case ASPEED_CLK_SDIO:
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ast2600_enable_extsdclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_EMMCCLK:
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ast2600_enable_emmcclk(priv->scu);
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break;
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case ASPEED_CLK_EMMC:
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ast2600_enable_extemmcclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_FSICLK:
|
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ast2600_enable_fsiclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_USBPORT1CLK:
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ast2600_enable_usbahclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_USBPORT2CLK:
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ast2600_enable_usbbhclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_YCLK:
|
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ast2600_enable_haceclk(priv->scu);
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break;
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case ASPEED_CLK_GATE_RSACLK:
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ast2600_enable_rsaclk(priv->scu);
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break;
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default:
|
|
debug("%s: unknown clk %ld\n", __func__, clk->id);
|
|
return -ENOENT;
|
|
}
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|
|
|
return 0;
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}
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|
|
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struct clk_ops ast2600_clk_ops = {
|
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.get_rate = ast2600_clk_get_rate,
|
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.set_rate = ast2600_clk_set_rate,
|
|
.enable = ast2600_clk_enable,
|
|
};
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|
|
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static int ast2600_clk_probe(struct udevice *dev)
|
|
{
|
|
struct ast2600_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->scu = devfdt_get_addr_ptr(dev);
|
|
if (IS_ERR(priv->scu))
|
|
return PTR_ERR(priv->scu);
|
|
|
|
ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig);
|
|
ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig);
|
|
ast2600_configure_mac12_clk(priv->scu);
|
|
ast2600_configure_mac34_clk(priv->scu);
|
|
ast2600_configure_rsa_ecc_clk(priv->scu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ast2600_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
|
|
if (ret)
|
|
debug("Warning: No reset driver: ret=%d\n", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct aspeed_clks {
|
|
ulong id;
|
|
const char *name;
|
|
};
|
|
|
|
static struct aspeed_clks aspeed_clk_names[] = {
|
|
{ ASPEED_CLK_HPLL, "hpll" },
|
|
{ ASPEED_CLK_MPLL, "mpll" },
|
|
{ ASPEED_CLK_APLL, "apll" },
|
|
{ ASPEED_CLK_EPLL, "epll" },
|
|
{ ASPEED_CLK_DPLL, "dpll" },
|
|
{ ASPEED_CLK_AHB, "hclk" },
|
|
{ ASPEED_CLK_APB1, "pclk1" },
|
|
{ ASPEED_CLK_APB2, "pclk2" },
|
|
{ ASPEED_CLK_BCLK, "bclk" },
|
|
{ ASPEED_CLK_UARTX, "uxclk" },
|
|
{ ASPEED_CLK_HUARTX, "huxclk" },
|
|
};
|
|
|
|
int soc_clk_dump(void)
|
|
{
|
|
struct udevice *dev;
|
|
struct clk clk;
|
|
unsigned long rate;
|
|
int i, ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu),
|
|
&dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
printf("Clk\t\tHz\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
|
|
clk.id = aspeed_clk_names[i].id;
|
|
ret = clk_request(dev, &clk);
|
|
if (ret < 0) {
|
|
debug("%s clk_request() failed: %d\n", __func__, ret);
|
|
continue;
|
|
}
|
|
|
|
ret = clk_get_rate(&clk);
|
|
rate = ret;
|
|
|
|
clk_free(&clk);
|
|
|
|
if (ret == -EINVAL) {
|
|
printf("clk ID %lu not supported yet\n",
|
|
aspeed_clk_names[i].id);
|
|
continue;
|
|
}
|
|
if (ret < 0) {
|
|
printf("%s %lu: get_rate err: %d\n", __func__,
|
|
aspeed_clk_names[i].id, ret);
|
|
continue;
|
|
}
|
|
|
|
printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name,
|
|
aspeed_clk_names[i].id, rate);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id ast2600_clk_ids[] = {
|
|
{ .compatible = "aspeed,ast2600-scu", },
|
|
{ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(aspeed_ast2600_scu) = {
|
|
.name = "aspeed_ast2600_scu",
|
|
.id = UCLASS_CLK,
|
|
.of_match = ast2600_clk_ids,
|
|
.priv_auto = sizeof(struct ast2600_clk_priv),
|
|
.ops = &ast2600_clk_ops,
|
|
.bind = ast2600_clk_bind,
|
|
.probe = ast2600_clk_probe,
|
|
};
|