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0b1b60c779
Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
264 lines
7.7 KiB
C
264 lines
7.7 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CLOCKS_OMAP5_H_
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#define _CLOCKS_OMAP5_H_
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#include <common.h>
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#include <asm/omap_common.h>
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/*
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* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
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* loop, allow for a minimum of 2 ms wait (in reality the wait will be
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* much more than that)
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*/
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#define LDELAY 1000000
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#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
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#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
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#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
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#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
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/* DPLL register offsets */
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#define CM_CLKMODE_DPLL 0
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#define CM_IDLEST_DPLL 0x4
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#define CM_AUTOIDLE_DPLL 0x8
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#define CM_CLKSEL_DPLL 0xC
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#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
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/* CM_DLL_CTRL */
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#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
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#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
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#define CM_DLL_CTRL_NO_OVERRIDE 0
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_FAST_RELOCK_BYPASS 6
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* SGX */
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#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
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#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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#define CM_CLKSEL_DCC_EN_SHIFT 22
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#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
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#define OMAP4_DPLL_MAX_N 127
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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#define CLKSEL_L3_SHIFT 4
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#define CLKSEL_L4_SHIFT 8
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#define CLKSEL_CORE_X2_DIV_1 0
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#define CLKSEL_L3_CORE_DIV_2 1
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#define CLKSEL_L4_L3_DIV_2 1
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/* CM_ABE_PLL_REF_CLKSEL */
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
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/* CM_BYPCLK_DPLL_IVA */
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
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#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
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/* CM_SHADOW_FREQ_CONFIG1 */
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#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
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#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
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#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
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#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
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#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_L4PER_GPIO4_CLKCTRL */
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#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_L3INIT_HSMMCn_CLKCTRL */
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
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/* CM_CAM_ISS_CLKCTRL */
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#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_DSS_DSS_CLKCTRL */
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#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
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/* CM_L3INIT_USBPHY_CLKCTRL */
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#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
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/* CM_MPU_MPU_CLKCTRL */
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
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/* CM_WKUPAON_SCRM_CLKCTRL */
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#define OPTFCLKEN_SCRM_PER_SHIFT 9
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#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
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#define OPTFCLKEN_SCRM_CORE_SHIFT 8
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#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
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/* CM_COREAON_IO_SRCOMP_CLKCTRL */
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#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
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#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
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/* PRM_RSTTIME */
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#define RSTTIME1_SHIFT 0
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#define RSTTIME1_MASK (0x3ff << 0)
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/* Clock frequencies */
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#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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#define OMAP_32K_CLK_FREQ 32768
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/* PRM_VC_VAL_BYPASS */
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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/* SMPS */
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_REG_ADDR_12_MPU 0x23
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#define SMPS_REG_ADDR_45_IVA 0x2B
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#define SMPS_REG_ADDR_8_CORE 0x37
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/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
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/* ES1.0 settings */
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#define VDD_MPU 1040
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#define VDD_MM 1040
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#define VDD_CORE 1040
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#define VDD_MPU_LOW 890
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#define VDD_MM_LOW 890
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#define VDD_CORE_LOW 890
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/* ES2.0 settings */
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#define VDD_MPU_ES2 1060
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#define VDD_MM_ES2 1025
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#define VDD_CORE_ES2 1040
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#define VDD_MPU_ES2_HIGH 1250
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#define VDD_MM_ES2_OD 1120
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#define VDD_MPU_ES2_LOW 880
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#define VDD_MM_ES2_LOW 880
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/* Standard offset is 0.5v expressed in uv */
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#define PALMAS_SMPS_BASE_VOLT_UV 500000
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/* TPS */
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#define TPS62361_I2C_SLAVE_ADDR 0x60
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#define TPS62361_REG_ADDR_SET0 0x0
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#define TPS62361_REG_ADDR_SET1 0x1
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#define TPS62361_REG_ADDR_SET2 0x2
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#define TPS62361_REG_ADDR_SET3 0x3
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#define TPS62361_REG_ADDR_CTRL 0x4
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#define TPS62361_REG_ADDR_TEMP 0x5
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#define TPS62361_REG_ADDR_RMP_CTRL 0x6
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#define TPS62361_REG_ADDR_CHIP_ID 0x8
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#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
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#define TPS62361_BASE_VOLT_MV 500
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#define TPS62361_VSEL0_GPIO 7
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/* Defines for DPLL setup */
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#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
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#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
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#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
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#define DPLL_NO_LOCK 0
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#define DPLL_LOCK 1
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/*
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* MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
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* 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
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* into microsec and passing the value.
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*/
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#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
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#endif /* _CLOCKS_OMAP5_H_ */
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