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https://github.com/AsahiLinux/u-boot
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49f5befafd
TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
71 lines
2.2 KiB
C
71 lines
2.2 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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sys_info_t sysinfo;
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char buf[32];
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size_t ddr_size;
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fsl_ddr_cfg_regs_t ddr_cfg_regs = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
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#endif
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
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.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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};
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return ddr_size;
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}
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