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620118403e
This commit moves source files as follows: arch/arm/cpu/arm920t/at91/* -> arch/arm/mach-at91/arm920t/* arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/* arch/arm/cpu/armv7/at91/* -> arch/arm/mach-at91/armv7/* arch/arm/cpu/at91-common/* -> arch/arm/mach-at91/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>
161 lines
5 KiB
C
161 lines
5 KiB
C
/*
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* (C) Copyright 2013 Atmel Corporation
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* Josh Wu <josh.wu@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_pio.h>
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unsigned int has_lcdc()
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{
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return 1;
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}
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void at91_serial0_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
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writel(1 << ATMEL_ID_USART0, &pmc->pcer);
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}
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void at91_serial1_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
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at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
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writel(1 << ATMEL_ID_USART1, &pmc->pcer);
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}
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void at91_serial2_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
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at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
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writel(1 << ATMEL_ID_USART2, &pmc->pcer);
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}
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void at91_serial3_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
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at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
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writel(1 << ATMEL_ID_USART3, &pmc->pcer);
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}
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void at91_seriald_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
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at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
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writel(1 << ATMEL_ID_SYS, &pmc->pcer);
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}
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#ifdef CONFIG_ATMEL_SPI
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
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/* Enable clock */
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writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
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if (cs_mask & (1 << 0))
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at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
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if (cs_mask & (1 << 1))
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at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
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if (cs_mask & (1 << 2))
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at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
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if (cs_mask & (1 << 3))
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at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
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}
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void at91_spi1_hw_init(unsigned long cs_mask)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
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at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
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at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
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/* Enable clock */
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writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
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if (cs_mask & (1 << 0))
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at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
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if (cs_mask & (1 << 1))
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at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
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if (cs_mask & (1 << 2))
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at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
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if (cs_mask & (1 << 3))
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at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
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}
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#endif
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void at91_mci_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
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at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
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at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
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at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
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at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
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at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
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writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
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}
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#ifdef CONFIG_LCD
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void at91_lcd_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
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at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
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at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
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at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
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at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
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writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
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}
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#endif
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