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On Amlogic Meson GXL/GXM, supplementary ethernet configuration registers were added to configure the internal RMII PHY interface. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __GXBB_H__
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#define __GXBB_H__
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#define GXBB_PERIPHS_BASE 0xc8834400
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#define GXBB_HIU_BASE 0xc883c000
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#define GXBB_ETH_BASE 0xc9410000
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/* Peripherals registers */
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#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
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/* GPIO registers 0 to 6 */
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#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
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#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
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#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
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#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
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#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
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#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
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#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56)
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#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57)
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#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
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#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GXBB_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
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#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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/* Clock gates */
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#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
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#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
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#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
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#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
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#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
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#define GXBB_GCLK_MPEG_1_ETH BIT(3)
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#endif /* __GXBB_H__ */
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