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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
298 lines
8 KiB
C
298 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
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#define __DRIVERS_PINCTRL_ROCKCHIP_H
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#include <linux/bitops.h>
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#include <linux/types.h>
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/**
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* Encode variants of iomux registers into a type variable
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*/
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#define IOMUX_GPIO_ONLY BIT(0)
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#define IOMUX_WIDTH_4BIT BIT(1)
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#define IOMUX_SOURCE_PMU BIT(2)
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#define IOMUX_UNROUTED BIT(3)
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#define IOMUX_WIDTH_3BIT BIT(4)
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#define IOMUX_8WIDTH_2BIT BIT(5)
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/**
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* Defined some common pins constants
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*/
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#define ROCKCHIP_PULL_BITS_PER_PIN 2
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#define ROCKCHIP_PULL_PINS_PER_REG 8
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#define ROCKCHIP_PULL_BANK_STRIDE 16
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#define ROCKCHIP_DRV_BITS_PER_PIN 2
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#define ROCKCHIP_DRV_PINS_PER_REG 8
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#define ROCKCHIP_DRV_BANK_STRIDE 16
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#define ROCKCHIP_DRV_3BITS_PER_PIN 3
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/**
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* @type: iomux variant using IOMUX_* constants
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
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*/
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struct rockchip_iomux {
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int type;
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int offset;
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};
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/**
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
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enum rockchip_pin_drv_type {
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DRV_TYPE_IO_DEFAULT = 0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_MAX
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};
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/**
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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enum rockchip_pin_pull_type {
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PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
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/**
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following drive strength
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* registers. if used chips own cal_drv func instead to calculate
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* registers offset, the variant could be ignored.
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*/
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struct rockchip_drv {
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enum rockchip_pin_drv_type drv_type;
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int offset;
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};
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/**
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* @priv: common pinctrl private basedata
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @recalced_mask: bits describing the mux recalced pins of per bank
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* @route_mask: bits describing the routing pins of per bank
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*/
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struct rockchip_pin_bank {
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struct rockchip_pinctrl_priv *priv;
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u32 pin_base;
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u8 nr_pins;
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char *name;
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u8 bank_num;
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struct rockchip_iomux iomux[4];
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struct rockchip_drv drv[4];
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enum rockchip_pin_pull_type pull_type[4];
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u32 recalced_mask;
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u32 route_mask;
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};
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#define PIN_BANK(id, pins, label) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = type0, .offset = -1 }, \
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{ .drv_type = type1, .offset = -1 }, \
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{ .drv_type = type2, .offset = -1 }, \
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{ .drv_type = type3, .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
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drv2, drv3, pull0, pull1, \
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pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = -1 }, \
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{ .drv_type = drv1, .offset = -1 }, \
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{ .drv_type = drv2, .offset = -1 }, \
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{ .drv_type = drv3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
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iom2, iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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offset2, offset3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = offset0 }, \
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{ .drv_type = drv1, .offset = offset1 }, \
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{ .drv_type = drv2, .offset = offset2 }, \
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{ .drv_type = drv3, .offset = offset3 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
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label, iom0, iom1, iom2, \
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iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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offset2, offset3, pull0, \
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pull1, pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = offset0 }, \
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{ .drv_type = drv1, .offset = offset1 }, \
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{ .drv_type = drv2, .offset = offset2 }, \
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{ .drv_type = drv3, .offset = offset3 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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/**
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* struct rockchip_mux_recalced_data: recalculate a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @reg: register offset.
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* @bit: index at register.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u32 reg;
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u8 bit;
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u8 mask;
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};
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/**
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* struct rockchip_mux_route_data: route a pin iomux data.
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* @bank_num: bank number.
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* @pin: index at register or used to calc index.
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* @func: the min pin.
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* @route_offset: the max pin.
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* @route_val: the register offset.
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*/
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struct rockchip_mux_route_data {
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u8 bank_num;
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u8 pin;
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u8 func;
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u32 route_offset;
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u32 route_val;
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};
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/**
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*/
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struct rockchip_pin_ctrl {
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struct rockchip_pin_bank *pin_banks;
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u32 nr_banks;
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u32 nr_pins;
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int grf_mux_offset;
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_recalced_data *iomux_recalced;
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u32 niomux_recalced;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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int (*set_mux)(struct rockchip_pin_bank *bank,
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int pin, int mux);
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int (*set_pull)(struct rockchip_pin_bank *bank,
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int pin_num, int pull);
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int (*set_drive)(struct rockchip_pin_bank *bank,
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int pin_num, int strength);
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int (*set_schmitt)(struct rockchip_pin_bank *bank,
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int pin_num, int enable);
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};
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/**
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*/
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struct rockchip_pinctrl_priv {
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struct rockchip_pin_ctrl *ctrl;
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struct regmap *regmap_base;
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struct regmap *regmap_pmu;
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};
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extern const struct pinctrl_ops rockchip_pinctrl_ops;
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int rockchip_pinctrl_probe(struct udevice *dev);
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void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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int *reg, u8 *bit, int *mask);
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bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
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int mux, u32 *reg, u32 *value);
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int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
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int rockchip_translate_drive_value(int type, int strength);
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int rockchip_translate_pull_value(int type, int pull);
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#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
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