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Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed-by: Ronen Shitrit <rshitrit@marvell.com> Acked-by: Stefan Rose <sr@denx.de> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <config.h>
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#include <asm/arch/kirkwood.h>
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#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
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#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
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/*
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* kw_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 kw_sdram_bar(enum memory_bank bank)
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{
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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if ((!enable) || (bank > BANK3))
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return 0;
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result = readl(KW_REG_CPUCS_WIN_BAR(bank));
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return result;
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}
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/*
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* kw_sdram_bs - reads SDRAM Bank size
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*/
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u32 kw_sdram_bs(enum memory_bank bank)
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{
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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if ((!enable) || (bank > BANK3))
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return 0;
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result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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result += 0x01000000;
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return result;
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}
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