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306fa01279
After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_EPU_H
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#define __FSL_EPU_H
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#include <asm/types.h>
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#define FSL_STRIDE_4B 4
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#define FSL_STRIDE_8B 8
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/* Block offsets */
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#define EPU_BLOCK_OFFSET 0x00000000
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/* EPGCR (Event Processor Global Control Register) */
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#define EPGCR 0x000
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/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
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#define EPEVTCR0 0x050
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#define EPEVTCR9 0x074
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#define EPEVTCR_STRIDE FSL_STRIDE_4B
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/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
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#define EPXTRIGCR 0x090
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/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
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#define EPIMCR0 0x100
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#define EPIMCR31 0x17C
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#define EPIMCR_STRIDE FSL_STRIDE_4B
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/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
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#define EPSMCR0 0x200
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#define EPSMCR15 0x278
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#define EPSMCR_STRIDE FSL_STRIDE_8B
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/* EPECR0-15 (Event Processor Event Control Registers) */
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#define EPECR0 0x300
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#define EPECR15 0x33C
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#define EPECR_STRIDE FSL_STRIDE_4B
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/* EPACR0-15 (Event Processor Action Control Registers) */
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#define EPACR0 0x400
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#define EPACR15 0x43C
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#define EPACR_STRIDE FSL_STRIDE_4B
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/* EPCCRi0-15 (Event Processor Counter Control Registers) */
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#define EPCCR0 0x800
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#define EPCCR15 0x83C
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#define EPCCR31 0x87C
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#define EPCCR_STRIDE FSL_STRIDE_4B
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/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
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#define EPCMPR0 0x900
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#define EPCMPR15 0x93C
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#define EPCMPR31 0x97C
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#define EPCMPR_STRIDE FSL_STRIDE_4B
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/* EPCTR0-31 (Event Processor Counter Register) */
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#define EPCTR0 0xA00
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#define EPCTR31 0xA7C
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#define EPCTR_STRIDE FSL_STRIDE_4B
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void fsl_epu_clean(void *epu_base);
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#endif
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