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4088f5fce8
Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright ASPEED Technology Inc.
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*/
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#ifndef __AST2600_I2C_H_
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#define __AST2600_I2C_H_
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struct ast2600_i2c_regs {
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u32 fun_ctrl;
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u32 ac_timing;
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u32 trx_buff;
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u32 icr;
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u32 ier;
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u32 isr;
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u32 cmd_sts;
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};
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/* 0x00 : I2CC Master/Slave Function Control Register */
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#define I2CC_SLAVE_ADDR_RX_EN BIT(20)
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#define I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
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#define I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0)) << 18)
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#define I2CC_BUS_AUTO_RELEASE BIT(17)
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#define I2CC_M_SDA_LOCK_EN BIT(16)
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#define I2CC_MULTI_MASTER_DIS BIT(15)
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#define I2CC_M_SCL_DRIVE_EN BIT(14)
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#define I2CC_MSB_STS BIT(9)
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#define I2CC_SDA_DRIVE_1T_EN BIT(8)
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#define I2CC_M_SDA_DRIVE_1T_EN BIT(7)
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#define I2CC_M_HIGH_SPEED_EN BIT(6)
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/* reserved 5 : 2 */
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#define I2CC_SLAVE_EN BIT(1)
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#define I2CC_MASTER_EN BIT(0)
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/* 0x04 : I2CD Clock and AC Timing Control Register #1 */
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/* Base register value. These bits are always set by the driver. */
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#define I2CD_CACTC_BASE 0xfff00300
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#define I2CD_TCKHIGH_SHIFT 16
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#define I2CD_TCKLOW_SHIFT 12
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#define I2CD_THDDAT_SHIFT 10
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#define I2CD_TO_DIV_SHIFT 8
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#define I2CD_BASE_DIV_SHIFT 0
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/* 0x08 : I2CC Master/Slave Transmit/Receive Byte Buffer Register */
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#define I2CC_TX_DIR_MASK GENMASK(31, 29)
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#define I2CC_SDA_OE BIT(28)
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#define I2CC_SDA_O BIT(27)
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#define I2CC_SCL_OE BIT(26)
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#define I2CC_SCL_O BIT(25)
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#define I2CC_SCL_LINE_STS BIT(18)
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#define I2CC_SDA_LINE_STS BIT(17)
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#define I2CC_BUS_BUSY_STS BIT(16)
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#define I2CC_GET_RX_BUFF(x) (((x) >> 8) & GENMASK(7, 0))
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/* 0x10 : I2CM Master Interrupt Control Register */
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/* 0x14 : I2CM Master Interrupt Status Register */
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#define I2CM_PKT_TIMEOUT BIT(18)
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#define I2CM_PKT_ERROR BIT(17)
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#define I2CM_PKT_DONE BIT(16)
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#define I2CM_BUS_RECOVER_FAIL BIT(15)
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#define I2CM_SDA_DL_TO BIT(14)
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#define I2CM_BUS_RECOVER BIT(13)
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#define I2CM_SMBUS_ALT BIT(12)
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#define I2CM_SCL_LOW_TO BIT(6)
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#define I2CM_ABNORMAL BIT(5)
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#define I2CM_NORMAL_STOP BIT(4)
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#define I2CM_ARBIT_LOSS BIT(3)
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#define I2CM_RX_DONE BIT(2)
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#define I2CM_TX_NAK BIT(1)
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#define I2CM_TX_ACK BIT(0)
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/* 0x18 : I2CM Master Command/Status Register */
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#define I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0)) << 24)
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#define I2CM_PKT_EN BIT(16)
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#define I2CM_SDA_OE_OUT_DIR BIT(15)
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#define I2CM_SDA_O_OUT_DIR BIT(14)
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#define I2CM_SCL_OE_OUT_DIR BIT(13)
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#define I2CM_SCL_O_OUT_DIR BIT(12)
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#define I2CM_RECOVER_CMD_EN BIT(11)
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#define I2CM_RX_DMA_EN BIT(9)
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#define I2CM_TX_DMA_EN BIT(8)
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/* Command Bit */
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#define I2CM_RX_BUFF_EN BIT(7)
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#define I2CM_TX_BUFF_EN BIT(6)
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#define I2CM_STOP_CMD BIT(5)
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#define I2CM_RX_CMD_LAST BIT(4)
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#define I2CM_RX_CMD BIT(3)
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#define I2CM_TX_CMD BIT(1)
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#define I2CM_START_CMD BIT(0)
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#define I2C_TIMEOUT_US 100000
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/* I2C Global Register */
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#define I2CG_ISR 0x00
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#define I2CG_SLAVE_ISR 0x04
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#define I2CG_OWNER 0x08
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#define I2CG_CTRL 0x0C
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#define I2CG_CLK_DIV_CTRL 0x10
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#define I2CG_SLAVE_PKT_NAK BIT(4)
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#define I2CG_M_S_SEPARATE_INTR BIT(3)
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#define I2CG_CTRL_NEW_REG BIT(2)
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#define I2CG_CTRL_NEW_CLK_DIV BIT(1)
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#define GLOBAL_INIT \
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(I2CG_SLAVE_PKT_NAK | \
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I2CG_CTRL_NEW_REG | \
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I2CG_CTRL_NEW_CLK_DIV)
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#define I2CCG_DIV_CTRL 0xc6411208
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#define GET_CLK1_DIV(x) ((x) & 0xff)
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#define GET_CLK2_DIV(x) (((x) >> 8) & 0xff)
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#define GET_CLK3_DIV(x) (((x) >> 16) & 0xff)
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#define GET_CLK4_DIV(x) (((x) >> 24) & 0xff)
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#endif /* __AST2600_I2C_H_ */
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