mirror of
https://github.com/AsahiLinux/u-boot
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320 lines
8.4 KiB
C
320 lines
8.4 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fec.h>
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#include <asm/immap.h>
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#include <config.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#undef MII_DEBUG
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#undef ET_DEBUG
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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struct fec_info_s *info = (struct fec_info_s *)dev->priv;
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if (setclear) {
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gpio->par_feci2c |=
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(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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if (info->iobase == CFG_FEC0_IOBASE)
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gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
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else
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gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
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} else {
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gpio->par_feci2c &=
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~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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if (info->iobase == CFG_FEC0_IOBASE)
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gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
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else
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gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
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}
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return 0;
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}
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#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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/* Make MII read/write commands for the FEC. */
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#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
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#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
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/* PHY identification */
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#define PHY_ID_LXT970 0x78100000 /* LXT970 */
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#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
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#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
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#define PHY_ID_QS6612 0x01814400 /* QS6612 */
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#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
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#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
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#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
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#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
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#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
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#define STR_ID_LXT970 "LXT970"
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#define STR_ID_LXT971 "LXT971"
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#define STR_ID_82555 "Intel82555"
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#define STR_ID_QS6612 "QS6612"
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#define STR_ID_AMD79C784 "AMD79C784"
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#define STR_ID_LSI80225 "LSI80225"
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#define STR_ID_LSI80225B "LSI80225/B"
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#define STR_ID_DP83848VV "N83848"
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#define STR_ID_DP83849 "N83849"
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet
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* This function is a subset of eth_init
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****************************************************************************
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*/
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void mii_reset(struct fec_info_s *info)
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{
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volatile fec_t *fecp = (fec_t *) (info->miibase);
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struct eth_device *dev;
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int i, miispd;
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u16 rst = 0;
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dev = eth_get_dev();
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miispd = (gd->bus_clk / 1000000) / 5;
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fecp->mscr = miispd << 1;
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miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
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for (i = 0; i < FEC_RESET_DELAY; ++i) {
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udelay(500);
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miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
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if ((rst & PHY_BMCR_RESET) == 0)
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break;
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}
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if (i == FEC_RESET_DELAY)
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printf("Mii reset timeout %d\n", i);
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}
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/* send command to phy using mii, wait for result */
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uint mii_send(uint mii_cmd)
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{
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struct fec_info_s *info;
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struct eth_device *dev;
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volatile fec_t *ep;
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uint mii_reply;
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int j = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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ep = (fec_t *) info->miibase;
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ep->mmfr = mii_cmd; /* command to phy */
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/* wait for mii complete */
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while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("MII not complete\n");
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return -1;
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}
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mii_reply = ep->mmfr; /* result from phy */
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ep->eir = FEC_EIR_MII; /* clear MII complete */
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#ifdef ET_DEBUG
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printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
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__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
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#endif
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return (mii_reply & 0xffff); /* data read from phy */
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}
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#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
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#if defined(CFG_DISCOVER_PHY)
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int mii_discover_phy(struct eth_device *dev)
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{
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#define MAX_PHY_PASSES 11
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struct fec_info_s *info = dev->priv;
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int phyaddr, pass;
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uint phyno, phytype;
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if (info->phyname_init)
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return info->phy_addr;
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phyaddr = -1; /* didn't find a PHY yet */
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for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
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if (pass > 1) {
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/* PHY may need more time to recover from reset.
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* The LXT970 needs 50ms typical, no maximum is
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* specified, so wait 10ms before try again.
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* With 11 passes this gives it 100ms to wake up.
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*/
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udelay(10000); /* wait 10ms */
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}
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
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#ifdef ET_DEBUG
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printf("PHY type 0x%x pass %d type\n", phytype, pass);
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#endif
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if (phytype != 0xffff) {
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phyaddr = phyno;
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phytype <<= 16;
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phytype |=
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mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
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switch (phytype & 0xffffffff) {
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case PHY_ID_DP83848VV:
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strcpy(info->phy_name,
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STR_ID_DP83848VV);
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info->phyname_init = 1;
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break;
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default:
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strcpy(info->phy_name, "unknown");
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info->phyname_init = 1;
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break;
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}
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#ifdef ET_DEBUG
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printf("PHY @ 0x%x pass %d type ", phyno, pass);
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switch (phytype & 0xffffffff) {
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case PHY_ID_DP83848VV:
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printf(STR_ID_DP83848VV);
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break;
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default:
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printf("0x%08x\n", phytype);
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break;
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}
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#endif
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}
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}
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}
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if (phyaddr < 0)
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printf("No PHY device found.\n");
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return phyaddr;
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}
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#endif /* CFG_DISCOVER_PHY */
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void mii_init(void) __attribute__((weak,alias("__mii_init")));
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void __mii_init(void)
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{
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volatile fec_t *fecp;
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struct fec_info_s *info;
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struct eth_device *dev;
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int miispd = 0, i = 0;
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u16 autoneg = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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fecp = (fec_t *) info->miibase;
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set MII speed */
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miispd = (gd->bus_clk / 1000000) / 5;
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fecp->mscr = miispd << 1;
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info->phy_addr = mii_discover_phy(dev);
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#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
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while (i < MCFFEC_TOUT_LOOP) {
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autoneg = 0;
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miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
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i++;
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if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
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break;
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udelay(500);
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}
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if (i >= MCFFEC_TOUT_LOOP) {
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printf("Auto Negotiation not complete\n");
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}
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/* adapt to the half/full speed settings */
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info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
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info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
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}
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/*****************************************************************************
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* Read and write a MII PHY register, routines used by MII Utilities
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*
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* FIXME: These routines are expected to return 0 on success, but mii_send
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* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
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* no PHY connected...
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* For now always return 0.
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* FIXME: These routines only work after calling eth_init() at least once!
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* Otherwise they hang in mii_send() !!! Sorry!
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*****************************************************************************/
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int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value)
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{
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short rdreg; /* register working value */
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#ifdef MII_DEBUG
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printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
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#endif
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rdreg = mii_send(mk_mii_read(addr, reg));
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*value = rdreg;
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#ifdef MII_DEBUG
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printf("0x%04x\n", *value);
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#endif
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return 0;
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}
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int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
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unsigned short value)
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{
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short rdreg; /* register working value */
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#ifdef MII_DEBUG
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printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
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#endif
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rdreg = mii_send(mk_mii_write(addr, reg, value));
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#ifdef MII_DEBUG
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printf("0x%04x\n", value);
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#endif
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return 0;
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}
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#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
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