u-boot/arch/riscv
Green Wan c552debbd8 riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31 16:35:55 +08:00
..
cpu riscv: cpu: fu740: clear feature disable CSR 2021-05-31 16:35:55 +08:00
dts riscv: dts: add SiFive Unmatched board support 2021-05-31 16:35:54 +08:00
include/asm riscv: cpu: fu740: Add support for cpu fu740 2021-05-31 16:35:53 +08:00
lib riscv: Drop USE_SPL_FIT_GENERATOR 2021-05-19 17:01:51 +08:00
config.mk kconfig / kbuild: Re-sync with Linux 4.19 2020-04-10 11:18:32 -04:00
Kconfig board: sifive: add HiFive Unmatched board support 2021-05-31 16:35:55 +08:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00