mirror of
https://github.com/AsahiLinux/u-boot
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ef5f5f6ca6
At present this enables a few arch-specific members of the global_data struct which are otherwise not part of the struct. As a result we have to use #ifdef in various places. The cost of always having these in the struct is small. Adjust things so that we can use compile-time code instead of #ifdefs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
319 lines
6.3 KiB
C
319 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/lib/cpu.c
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*/
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#include <common.h>
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#include <bootstage.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <init.h>
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#include <log.h>
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#include <malloc.h>
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#include <syscon.h>
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#include <acpi/acpi_s3.h>
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#include <acpi/acpi_table.h>
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#include <asm/acpi.h>
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#include <asm/control_regs.h>
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#include <asm/coreboot_tables.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/microcode.h>
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#include <asm/mp.h>
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#include <asm/mrccache.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/interrupt.h>
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#include <asm/tables.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_TPL_BUILD
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static const char *const x86_vendor_name[] = {
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[X86_VENDOR_INTEL] = "Intel",
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[X86_VENDOR_CYRIX] = "Cyrix",
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[X86_VENDOR_AMD] = "AMD",
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[X86_VENDOR_UMC] = "UMC",
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[X86_VENDOR_NEXGEN] = "NexGen",
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[X86_VENDOR_CENTAUR] = "Centaur",
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[X86_VENDOR_RISE] = "Rise",
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[X86_VENDOR_TRANSMETA] = "Transmeta",
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[X86_VENDOR_NSC] = "NSC",
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[X86_VENDOR_SIS] = "SiS",
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};
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#endif
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int __weak x86_cleanup_before_linux(void)
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{
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#ifdef CONFIG_BOOTSTAGE_STASH
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bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
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CONFIG_BOOTSTAGE_STASH_SIZE);
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#endif
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return 0;
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}
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int x86_init_cache(void)
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{
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enable_caches();
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return 0;
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}
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int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
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void flush_cache(unsigned long dummy1, unsigned long dummy2)
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{
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asm("wbinvd\n");
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}
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/* Define these functions to allow ehch-hcd to function */
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void dcache_enable(void)
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{
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enable_caches();
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}
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void dcache_disable(void)
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{
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disable_caches();
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 1;
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}
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#ifndef CONFIG_TPL_BUILD
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const char *cpu_vendor_name(int vendor)
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{
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const char *name;
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name = "<invalid cpu vendor>";
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if (vendor < ARRAY_SIZE(x86_vendor_name) &&
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x86_vendor_name[vendor])
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name = x86_vendor_name[vendor];
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return name;
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}
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#endif
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char *cpu_get_name(char *name)
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{
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unsigned int *name_as_ints = (unsigned int *)name;
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struct cpuid_result regs;
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char *ptr;
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int i;
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/* This bit adds up to 48 bytes */
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for (i = 0; i < 3; i++) {
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regs = cpuid(0x80000002 + i);
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name_as_ints[i * 4 + 0] = regs.eax;
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name_as_ints[i * 4 + 1] = regs.ebx;
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name_as_ints[i * 4 + 2] = regs.ecx;
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name_as_ints[i * 4 + 3] = regs.edx;
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}
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name[CPU_MAX_NAME_LEN - 1] = '\0';
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/* Skip leading spaces. */
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ptr = name;
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while (*ptr == ' ')
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ptr++;
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return ptr;
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}
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int default_print_cpuinfo(void)
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{
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printf("CPU: %s, vendor %s, device %xh\n",
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cpu_has_64bit() ? "x86_64" : "x86",
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cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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debug("ACPI previous sleep state: %s\n",
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acpi_ss_string(gd->arch.prev_sleep_state));
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}
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return 0;
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}
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void show_boot_progress(int val)
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{
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outb(val, POST_PORT);
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}
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#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
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/*
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* Implement a weak default function for boards that optionally
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* need to clean up the system before jumping to the kernel.
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*/
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__weak void board_final_cleanup(void)
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{
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}
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int last_stage_init(void)
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{
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struct acpi_fadt __maybe_unused *fadt;
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board_final_cleanup();
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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fadt = acpi_find_fadt();
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if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
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acpi_resume(fadt);
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}
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write_tables();
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#ifdef CONFIG_GENERATE_ACPI_TABLE
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fadt = acpi_find_fadt();
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/* Don't touch ACPI hardware on HW reduced platforms */
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if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
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/*
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* Other than waiting for OSPM to request us to switch to ACPI
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* mode, do it by ourselves, since SMI will not be triggered.
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*/
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enter_acpi_mode(fadt->pm1a_cnt_blk);
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}
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#endif
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return 0;
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}
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#endif
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static int x86_init_cpus(void)
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{
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#ifdef CONFIG_SMP
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debug("Init additional CPUs\n");
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x86_mp_init();
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#else
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struct udevice *dev;
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/*
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* This causes the cpu-x86 driver to be probed.
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* We don't check return value here as we want to allow boards
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* which have not been converted to use cpu uclass driver to boot.
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*/
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uclass_first_device(UCLASS_CPU, &dev);
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#endif
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return 0;
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}
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int cpu_init_r(void)
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{
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struct udevice *dev;
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int ret;
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if (!ll_boot_init()) {
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uclass_first_device(UCLASS_PCI, &dev);
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return 0;
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}
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ret = x86_init_cpus();
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if (ret)
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return ret;
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/*
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* Set up the northbridge, PCH and LPC if available. Note that these
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* may have had some limited pre-relocation init if they were probed
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* before relocation, but this is post relocation.
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*/
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uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
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uclass_first_device(UCLASS_PCH, &dev);
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uclass_first_device(UCLASS_LPC, &dev);
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/* Set up pin control if available */
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ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
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debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
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return 0;
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}
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#ifndef CONFIG_EFI_STUB
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int reserve_arch(void)
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{
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#ifdef CONFIG_ENABLE_MRC_CACHE
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mrccache_reserve();
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#endif
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#ifdef CONFIG_SEABIOS
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high_table_reserve();
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#endif
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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acpi_s3_reserve();
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if (IS_ENABLED(CONFIG_HAVE_FSP)) {
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/*
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* Save stack address to CMOS so that at next S3 boot,
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* we can use it as the stack address for fsp_contiue()
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*/
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fsp_save_s3_stack();
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}
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}
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return 0;
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}
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#endif
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long detect_coreboot_table_at(ulong start, ulong size)
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{
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u32 *ptr, *end;
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size /= 4;
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for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
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if (*ptr == 0x4f49424c) /* "LBIO" */
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return (long)ptr;
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}
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return -ENOENT;
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}
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long locate_coreboot_table(void)
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{
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long addr;
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/* We look for LBIO in the first 4K of RAM and again at 960KB */
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addr = detect_coreboot_table_at(0x0, 0x1000);
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if (addr < 0)
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addr = detect_coreboot_table_at(0xf0000, 0x1000);
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return addr;
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}
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