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c28d3bbe96
To avoid board-specific code accessing the mb862xx registers directly, the public function mb862xx_probe() has been introduced. Furthermore, the "Change of Clock Frequency" and "Set Memory I/F Mode" registers are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR, respectively. The BSPs for the socrates and lwmon5 boards have been adapted accordingly. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/*
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* (C) Copyright 2007
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* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
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*/
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#ifndef _MB862XX_H_
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#define _MB862XX_H_
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#define PCI_VENDOR_ID_FUJITSU 0x10CF
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#define PCI_DEVICE_ID_CORAL_P 0x2019
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#define PCI_DEVICE_ID_CORAL_PA 0x201E
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#define MB862XX_TYPE_LIME 0x1
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#define GC_HOST_BASE 0x01fc0000
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#define GC_DISP_BASE 0x01fd0000
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#define GC_DRAW_BASE 0x01ff0000
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/* Host interface registers */
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#define GC_SRST 0x0000002c
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#define GC_CCF 0x00000038
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#define GC_CID 0x000000f0
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#define GC_MMR 0x0000fffc
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/*
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* Display Controller registers
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* _A means the offset is aligned, we use these for boards
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* with 8-/16-bit GDC access not working or buggy.
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*/
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#define GC_DCM0 0x00000000
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#define GC_HTP_A 0x00000004
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#define GC_HTP 0x00000006
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#define GC_HDB_HDP_A 0x00000008
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#define GC_HDP 0x00000008
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#define GC_HDB 0x0000000a
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#define GC_VSW_HSW_HSP_A 0x0000000c
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#define GC_HSP 0x0000000c
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#define GC_HSW 0x0000000e
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#define GC_VSW 0x0000000f
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#define GC_VTR_A 0x00000010
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#define GC_VTR 0x00000012
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#define GC_VDP_VSP_A 0x00000014
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#define GC_VSP 0x00000014
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#define GC_VDP 0x00000016
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#define GC_WY_WX 0x00000018
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#define GC_WH_WW 0x0000001c
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#define GC_L0M 0x00000020
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#define GC_L0OA0 0x00000024
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#define GC_L0DA0 0x00000028
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#define GC_L0DY_L0DX 0x0000002c
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#define GC_L2M 0x00000040
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#define GC_L2OA0 0x00000044
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#define GC_L2DA0 0x00000048
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#define GC_L2OA1 0x0000004c
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#define GC_L2DA1 0x00000050
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#define GC_L2DX 0x00000054
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#define GC_L2DY 0x00000056
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#define GC_DCM1 0x00000100
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#define GC_DCM2 0x00000104
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#define GC_DCM3 0x00000108
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#define GC_L0EM 0x00000110
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#define GC_L0WY_L0WX 0x00000114
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#define GC_L0WH_L0WW 0x00000118
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#define GC_L2EM 0x00000130
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#define GC_L2WX 0x00000134
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#define GC_L2WY 0x00000136
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#define GC_L2WW 0x00000138
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#define GC_L2WH 0x0000013a
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#define GC_L0PAL0 0x00000400
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/* Drawing registers */
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#define GC_CTR 0x00000400
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#define GC_IFCNT 0x00000408
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#define GC_FBR 0x00000440
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#define GC_XRES 0x00000444
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#define GC_CXMIN 0x00000454
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#define GC_CXMAX 0x00000458
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#define GC_CYMIN 0x0000045c
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#define GC_CYMAX 0x00000460
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#define GC_FC 0x00000480
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#define GC_BC 0x00000484
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#define GC_FIFO 0x000004a0
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#define GC_REV 0x00008084
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#define GC_GEO_FIFO 0x00008400
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typedef struct {
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unsigned int index;
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unsigned int value;
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} gdc_regs;
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int mb862xx_probe(unsigned int addr);
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const gdc_regs *board_get_regs (void);
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unsigned int board_video_init (void);
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void board_backlight_switch(int);
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#endif /* _MB862XX_H_ */
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