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552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
139 lines
3 KiB
C
139 lines
3 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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/* General purpose timers registers */
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struct mxc_gpt {
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unsigned int control;
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unsigned int prescaler;
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unsigned int status;
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unsigned int nouse[6];
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unsigned int counter;
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};
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static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
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#define GPTCR_FRR (1 << 9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
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#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
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#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
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#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
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#define GPTCR_TEN 1 /* Timer enable */
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#define GPTPR_PRESCALER24M_SHIFT 12
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#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
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DECLARE_GLOBAL_DATA_PTR;
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static inline int gpt_has_clk_source_osc(void)
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{
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#if defined(CONFIG_MX6)
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if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
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is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
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is_mx6ull() || is_mx6sll())
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return 1;
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return 0;
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#else
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return 0;
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#endif
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}
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static inline ulong gpt_get_clk(void)
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{
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#ifdef CONFIG_MXC_GPT_HCLK
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if (gpt_has_clk_source_osc())
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return MXC_HCLK >> 3;
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else
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return mxc_get_clock(MXC_IPG_PERCLK);
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#else
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return MXC_CLK32;
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#endif
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}
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int timer_init(void)
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{
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int i;
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/* setup GP Timer 1 */
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__raw_writel(GPTCR_SWR, &cur_gpt->control);
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/* We have no udelay by now */
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for (i = 0; i < 100; i++)
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__raw_writel(0, &cur_gpt->control);
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i = __raw_readl(&cur_gpt->control);
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i &= ~GPTCR_CLKSOURCE_MASK;
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#ifdef CONFIG_MXC_GPT_HCLK
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if (gpt_has_clk_source_osc()) {
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i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
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/*
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* For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
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* Enable bit and prescaler
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*/
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if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
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is_mx6sll()) {
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i |= GPTCR_24MEN;
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/* Produce 3Mhz clock */
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__raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
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&cur_gpt->prescaler);
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}
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} else {
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i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
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}
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#else
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__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
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i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
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#endif
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__raw_writel(i, &cur_gpt->control);
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return __raw_readl(&cur_gpt->counter); /* current tick value */
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gpt_get_clk();
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}
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/*
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* This function is intended for SHORT delays only.
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* It will overflow at around 10 seconds @ 400MHz,
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* or 20 seconds @ 200MHz.
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*/
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unsigned long usec2ticks(unsigned long _usec)
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{
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unsigned long long usec = _usec;
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usec *= get_tbclk();
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usec += 999999;
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do_div(usec, 1000000);
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return usec;
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}
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