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d59c557049
Erratum: A-004034 Affects: SRIO Description: During port initialization, the SRIO port performs lane synchronization (detecting valid symbols on a lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An SRIO port configured as a 4x port may see one of these scenarios: 1. One or more lanes fails to achieve lane synchronization. Depending on which lanes fail, this may result in downtraining from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane). 2. The link may fail to achieve lane alignment as a 4x, even though all 4 lanes achieve lane synchronization, and downtrain to a 1x. An SRIO port configured as a 1x port may fail to complete port initialization (PnESCSR[PU] never deasserts) because of scenario 1. Impact: SRIO port may downtrain to 1x, or may fail to complete link initialization. Once a port completes link initialization successfully, it will operate normally. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
141 lines
4.5 KiB
C
141 lines
4.5 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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extern int enable_cpu_a011_workaround;
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#endif
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__maybe_unused u32 svr = get_svr();
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#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
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if (IS_SVR_REV(svr, 1, 0)) {
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switch (SVR_SOC_VER(svr)) {
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case SVR_P1013:
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case SVR_P1022:
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puts("Work-around for Erratum SATA A001 enabled\n");
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}
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}
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
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puts("Work-around for Erratum SERDES8 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
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puts("Work-around for Erratum SERDES9 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
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puts("Work-around for Erratum SERDES-A005 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum CPU22 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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/*
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* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
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* The SVR has been checked by cpu_init_r().
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*/
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if (enable_cpu_a011_workaround)
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puts("Work-around for Erratum CPU-A011 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
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puts("Work-around for Erratum CPU-A003999 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
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puts("Work-around for Erratum DDR-A003473 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
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puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
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puts("Work-around for Erratum ESDHC111 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
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puts("Work-around for Erratum ESDHC135 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum ESDHC13 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
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puts("Work-around for Erratum ESDHC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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puts("Work-around for Erratum CPC-A002 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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puts("Work-around for Erratum CPC-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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puts("Work-around for Erratum ELBC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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puts("Work-around for Erratum DDR-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
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puts("Work-around for Erratum DDR115 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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puts("Work-around for Erratum DDR111 enabled\n");
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puts("Work-around for Erratum DDR134 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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puts("Work-around for Erratum IFC-A002769 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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puts("Work-around for Erratum P1010-A003549 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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puts("Work-around for Erratum IFC A-003399 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG DDR120 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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puts("Work-around for Erratum NMG_LBC103 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG ETSEC129 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
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puts("Work-around for Erratum A004510 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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puts("Work-around for Erratum SRIO-A004034 enabled\n");
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#endif
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return 0;
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}
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U_BOOT_CMD(
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errata, 1, 0, do_errata,
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"Report errata workarounds",
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""
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);
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