u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c
Rick Chen 48cbf62460 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE
to boot from ram which allow the board to override the fdt
address originally.

But after this patch
riscv: save hart ID and device tree passed by prior boot stage
It provide prior_stage_fdt_address which offer a temporary
memory address to keep the dtb address passing from loader(gdb)
to u-boot with a1.

So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and
can be removed. And it also somehow may corrupted BBL if it
was be arranged in CONFIG_SYS_SDRAM_BASE.

In board_fdt_blob_setup()
When boting from ram:
prior_stage_fdt_address will be use to reserved dtb temporarily.

When booting from ROM:
dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base.
Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM)
which is provided by HW.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2018-12-05 14:14:16 +08:00

107 lines
2.1 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <common.h>
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
#endif
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
extern phys_addr_t prior_stage_fdt_address;
/*
* Miscellaneous platform dependent initializations
*/
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
return 0;
}
int dram_init(void)
{
unsigned long sdram_base = PHYS_SDRAM_0;
unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
unsigned long actual_size;
actual_size = get_ram_size((void *)sdram_base, expected_size);
gd->ram_size = actual_size;
if (expected_size != actual_size) {
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
}
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
#endif
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
return 0;
}
void *board_fdt_blob_setup(void)
{
void **ptr = (void *)&prior_stage_fdt_address;
if (fdt_magic(*ptr) == FDT_MAGIC)
return (void *)*ptr;
return (void *)CONFIG_SYS_FDT_BASE;
}
int smc_init(void)
{
int node = -1;
const char *compat = "andestech,atfsmc020";
void *blob = (void *)gd->fdt_blob;
fdt_addr_t addr;
struct ftsmc020_bank *regs;
node = fdt_node_offset_by_compatible(blob, -1, compat);
if (node < 0)
return -FDT_ERR_NOTFOUND;
addr = fdtdec_get_addr(blob, node, "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
regs = (struct ftsmc020_bank *)addr;
regs->cr &= ~FTSMC020_BANK_WPROT;
return 0;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
smc_init();
return 0;
}
#endif