u-boot/arch/arm/dts/mt8183.dtsi
Fabien Parent 18380437c1 ARM: mediatek: Add MT8183 support
Add the MT8183 SoC support.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-03-20 16:24:27 -04:00

274 lines
6 KiB
Text

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Copyright (C) 2021 BayLibre, SAS
* Author: Ben Ho <ben.ho@mediatek.com>
* Erin Lo <erin.lo@mediatek.com>
* Fabien Parent <fparent@baylibre.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt8183";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x002>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x003>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt",
"mediatek,wdt";
reg = <0 0x10007000 0 0x100>;
status = "disabled";
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c100000 0 0x200000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
};
};
sysirq: interrupt-controller@c530a80 {
compatible = "mediatek,mt8183-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x0c530a80 0 0x50>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8183-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8183-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8183-uart",
"mediatek,hsuart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <26000000>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
<&infracfg CLK_INFRA_MSDC0>,
<&infracfg CLK_INFRA_MSDC0_SCK>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
u3phy: usb-phy@11f40000 {
compatible = "mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port0: usb-phy2@11f40000 {
reg = <0 0x11f40000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy3@11f40700 {
reg = <0 0x11f40700 0 0x900>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
usb: usb@11200000 {
compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
reg = <0 0x11200000 0 0x3e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>;
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
ssusb: ssusb@11200000 {
compatible = "mediatek,ssusb";
reg = <0 0x11200000 0 0x3e00>;
reg-names = "mac";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
usb_host: xhci@11200000 {
compatible = "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
};
};