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270 lines
14 KiB
C
270 lines
14 KiB
C
/*
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* File: include/asm-blackfin/mach-bf561/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
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#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
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# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
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#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
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/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
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#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
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/* Testset instructions restricted to 32-bit aligned memory locations */
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#define ANOMALY_05000120 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Erroneous exception when enabling cache */
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#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
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/* Signbits instruction not functional under certain conditions */
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#define ANOMALY_05000127 (1)
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/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
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#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
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/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
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#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
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/* Stall in multi-unit DMA operations */
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#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
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/* Allowing the SPORT RX FIFO to fill will cause an overflow */
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#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
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/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
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#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
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/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
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#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
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/* DMA and TESTSET conflict when both are accessing external memory */
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#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
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/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
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#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
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/* MDMA may lose the first few words of a descriptor chain */
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#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
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/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
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#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
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/* IMDMA S1/D1 channel may stall */
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#define ANOMALY_05000149 (1)
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/* DMA engine may lose data due to incorrect handshaking */
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#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
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/* DMA stalls when all three controllers read data from the same source */
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#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
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/* Execution stall when executing in L2 and doing external accesses */
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#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
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/* Frame Delay in SPORT Multichannel Mode */
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#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
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/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
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#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
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/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
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#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
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/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
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/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
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#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
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/* A read from external memory may return a wrong value with data cache enabled */
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#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
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/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
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#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
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/* DMEM_CONTROL<12> is not set on Reset */
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#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
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/* SPORT transmit data is not gated by external frame sync in certain conditions */
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#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
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/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
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#define ANOMALY_05000166 (1)
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/* Turning Serial Ports on with External Frame Syncs */
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#define ANOMALY_05000167 (1)
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/* SDRAM auto-refresh and subsequent Power Ups */
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#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
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/* DATA CPLB page miss can result in lost write-through cache data writes */
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#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
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/* Boot-ROM code modifies SICA_IWRx wakeup registers */
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#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
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/* DSPID register values incorrect */
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#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
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/* DMA vs Core accesses to external memory */
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#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
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/* Cache Fill Buffer Data lost */
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#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
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/* Overlapping Sequencer and Memory Stalls */
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#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
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/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
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#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
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/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
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#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* Disabling the PPI resets the PPI configuration registers */
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#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
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/* IMDMA does not operate to full speed for 600MHz and higher devices */
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#define ANOMALY_05000182 (1)
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/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
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#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
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/* PPI TX Mode with 2 External Frame Syncs */
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#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
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/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
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#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
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/* IMDMA Corrupted Data after a Halt */
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#define ANOMALY_05000187 (1)
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/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
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#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
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/* False Protection Exceptions */
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#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
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/* PPI not functional at core voltage < 1Volt */
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#define ANOMALY_05000190 (1)
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/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
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#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
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/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
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#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
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/* Restarting SPORT in Specific Modes May Cause Data Corruption */
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#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
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/* Failing MMR Accesses When Stalled by Preceding Memory Read */
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#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
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/* Current DMA Address Shows Wrong Value During Carry Fix */
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#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
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/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
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#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
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/* Possible Infinite Stall with Specific Dual-DAG Situation */
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#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
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/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
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#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
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/* Specific sequence that can cause DMA error or DMA stopping */
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#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
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/* Recovery from "Brown-Out" Condition */
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#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
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/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
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#define ANOMALY_05000208 (1)
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/* Speed Path in Computational Unit Affects Certain Instructions */
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#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
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/* UART TX Interrupt Masked Erroneously */
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#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
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/* NMI Event at Boot Time Results in Unpredictable State */
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#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
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/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
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#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
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/* Incorrect Pulse-Width of UART Start Bit */
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#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
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/* Scratchpad Memory Bank Reads May Return Incorrect Data */
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#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
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/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
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#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
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/* UART STB Bit Incorrectly Affects Receiver Setting */
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#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
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/* SPORT data transmit lines are incorrectly driven in multichannel mode */
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#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
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/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
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#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
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/* TESTSET operation forces stall on the other core */
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#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
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/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
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#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
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/* Exception Not Generated for MMR Accesses in Reserved Region */
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#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
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/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
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#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
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/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
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#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
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/* ICPLB_STATUS MMR Register May Be Corrupted */
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#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
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/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
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/* Stores To Data Cache May Be Lost */
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#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
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/* Hardware Loop Corrupted When Taking an ICPLB Exception */
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#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
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/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
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#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
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/* IMDMA destination IRQ status must be read prior to using IMDMA */
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#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
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/* IMDMA may corrupt data under certain conditions */
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#define ANOMALY_05000267 (1)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
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#define ANOMALY_05000269 (1)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (1)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Data cache write back to external synchronous memory may be lost */
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#define ANOMALY_05000274 (1)
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/* PPI Timing and Sampling Information Updates */
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#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
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/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
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#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
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/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
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/* False Hardware Error Exception When ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
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/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
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#define ANOMALY_05000283 (1)
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/* A read will receive incorrect data under certain conditions */
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#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
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#define ANOMALY_05000302 (1)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* PPI Is Level-Sensitive on First Transfer */
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#define ANOMALY_05000313 (1)
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/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
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#define ANOMALY_05000315 (1)
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/* PF2 Output Remains Asserted After SPI Master Boot */
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#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
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/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
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#define ANOMALY_05000323 (1)
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/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
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#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
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/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
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#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
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/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
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#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
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/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
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#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
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/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
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#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
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/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
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#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* Conflicting Column Address Widths Causes SDRAM Errors */
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#define ANOMALY_05000362 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#endif
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