mirror of
https://github.com/AsahiLinux/u-boot
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e1a0cafcfb
At present the uclass stored frame buffer size is set to a hard coded value, but we can calculate the correct value based on what is configured. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Modified from coreboot bochs.c
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*/
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#define LOG_CATEGORY UCLASS_VIDEO
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pci.h>
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#include <video.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include "bochs.h"
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static int xsize = CONFIG_VIDEO_BOCHS_SIZE_X;
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static int ysize = CONFIG_VIDEO_BOCHS_SIZE_Y;
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static void bochs_write(void *mmio, int index, int val)
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{
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writew(val, mmio + MMIO_BASE + index * 2);
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}
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static int bochs_read(void *mmio, int index)
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{
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return readw(mmio + MMIO_BASE + index * 2);
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}
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static void bochs_vga_write(void *mmio, int index, uint8_t val)
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{
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writeb(val, mmio + VGA_BASE + index);
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}
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static int bochs_init_fb(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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ulong fb;
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void *mmio;
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int id, mem;
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log_debug("probing %s at PCI %x\n", dev->name, dm_pci_get_bdf(dev));
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fb = dm_pci_read_bar32(dev, 0);
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if (!fb)
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return log_msg_ret("fb", -EIO);
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/* MMIO bar supported since qemu 3.0+ */
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mmio = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE,
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PCI_REGION_MEM);
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if (!mmio)
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return log_msg_ret("map", -EIO);
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/* bochs dispi detection */
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id = bochs_read(mmio, INDEX_ID);
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if ((id & 0xfff0) != ID0) {
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log_debug("ID mismatch\n");
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return -EPROTONOSUPPORT;
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}
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mem = bochs_read(mmio, INDEX_VIDEO_MEMORY_64K) * SZ_64K;
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log_debug("QEMU VGA: bochs @ %p: %d MiB FB at %lx\n", mmio, mem / SZ_1M,
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fb);
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uc_priv->xsize = xsize;
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uc_priv->ysize = ysize;
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uc_priv->bpix = VIDEO_BPP32;
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/* setup video mode */
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bochs_write(mmio, INDEX_ENABLE, 0);
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bochs_write(mmio, INDEX_BANK, 0);
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bochs_write(mmio, INDEX_BPP, VNBITS(uc_priv->bpix));
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bochs_write(mmio, INDEX_XRES, xsize);
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bochs_write(mmio, INDEX_YRES, ysize);
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bochs_write(mmio, INDEX_VIRT_WIDTH, xsize);
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bochs_write(mmio, INDEX_VIRT_HEIGHT, ysize);
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bochs_write(mmio, INDEX_X_OFFSET, 0);
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bochs_write(mmio, INDEX_Y_OFFSET, 0);
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bochs_write(mmio, INDEX_ENABLE, ENABLED | LFB_ENABLED);
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/* disable blanking */
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bochs_vga_write(mmio, VGA_ATT_W - VGA_INDEX, VGA_AR_ENABLE_DISPLAY);
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plat->base = fb;
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return 0;
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}
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static int bochs_video_probe(struct udevice *dev)
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{
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int ret;
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ret = bochs_init_fb(dev);
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if (ret)
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return log_ret(ret);
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return 0;
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}
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static int bochs_video_bind(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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/* Set the frame buffer size per configuration */
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uc_plat->size = xsize * ysize * 32 / 8;
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log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
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return 0;
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}
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U_BOOT_DRIVER(bochs_video) = {
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.name = "bochs_video",
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.id = UCLASS_VIDEO,
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.bind = bochs_video_bind,
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.probe = bochs_video_probe,
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};
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static struct pci_device_id bochs_video_supported[] = {
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{ PCI_DEVICE(0x1234, 0x1111) },
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{ },
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};
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U_BOOT_PCI_DEVICE(bochs_video, bochs_video_supported);
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