mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 21:24:29 +00:00
6875149740
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
57 lines
1.2 KiB
Text
57 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* P2020 Silicon/SoC Device Tree Source (post include)
|
|
*
|
|
* Copyright 2013 Freescale Semiconductor Inc.
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "fsl,p2020-immr", "simple-bus";
|
|
bus-frequency = <0x0>;
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <4>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "fsl,mpic";
|
|
device_type = "open-pic";
|
|
big-endian;
|
|
single-cpu-affinity;
|
|
last-interrupt-source = <255>;
|
|
};
|
|
};
|
|
|
|
/* PCIe controller base address 0x8000 */
|
|
&pci2 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
|
law_trgt_if = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
};
|
|
|
|
/* PCIe controller base address 0x9000 */
|
|
&pci1 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
|
law_trgt_if = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
};
|
|
|
|
/* PCIe controller base address 0xa000 */
|
|
&pci0 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
|
law_trgt_if = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
};
|