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MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
29 lines
696 B
Text
29 lines
696 B
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* MPC8548CDS Device Tree Source
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*
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* Copyright 2006 - 2012 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/include/ "mpc8548.dtsi"
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/ {
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model = "fsl,MPC8548CDS";
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compatible = "fsl,MPC8548CDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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soc: soc8548@e0000000 {
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ranges = <0x0 0x0 0xe0000000 0x100000>;
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};
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pcie: pcie@e000a000 {
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reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
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0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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};
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/include/ "mpc8548-post.dtsi"
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