mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
295 lines
8.8 KiB
C
295 lines
8.8 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __WM8994_REGISTERS_H__
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#define __WM8994_REGISTERS_H__
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/*
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* Register values.
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*/
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#define WM8994_SOFTWARE_RESET 0x00
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#define WM8994_POWER_MANAGEMENT_1 0x01
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#define WM8994_POWER_MANAGEMENT_2 0x02
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#define WM8994_POWER_MANAGEMENT_5 0x05
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#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
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#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
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#define WM8994_OUTPUT_MIXER_1 0x2D
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#define WM8994_OUTPUT_MIXER_2 0x2E
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#define WM8994_CHARGE_PUMP_1 0x4C
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#define WM8994_DC_SERVO_1 0x54
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#define WM8994_ANALOGUE_HP_1 0x60
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#define WM8994_CHIP_REVISION 0x100
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#define WM8994_AIF1_CLOCKING_1 0x200
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#define WM8994_AIF1_CLOCKING_2 0x201
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#define WM8994_AIF2_CLOCKING_1 0x204
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#define WM8994_CLOCKING_1 0x208
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#define WM8994_CLOCKING_2 0x209
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#define WM8994_AIF1_RATE 0x210
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#define WM8994_AIF2_RATE 0x211
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#define WM8994_RATE_STATUS 0x212
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#define WM8994_AIF1_CONTROL_1 0x300
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#define WM8994_AIF1_CONTROL_2 0x301
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#define WM8994_AIF1_MASTER_SLAVE 0x302
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#define WM8994_AIF1_BCLK 0x303
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#define WM8994_AIF2_CONTROL_1 0x310
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#define WM8994_AIF2_CONTROL_2 0x311
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#define WM8994_AIF2_MASTER_SLAVE 0x312
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#define WM8994_AIF2_BCLK 0x313
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#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
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#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
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#define WM8994_AIF2_DAC_FILTERS_1 0x520
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#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
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#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
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#define WM8994_DAC1_LEFT_VOLUME 0x610
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#define WM8994_DAC1_RIGHT_VOLUME 0x611
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#define WM8994_GPIO_3 0x702
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#define WM8994_GPIO_4 0x703
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#define WM8994_GPIO_5 0x704
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/*
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* Field Definitions.
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*/
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/*
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* R0 (0x00) - Software Reset
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*/
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/* SW_RESET */
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#define WM8994_SW_RESET 1
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/*
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* R1 (0x01) - Power Management (1)
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*/
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/* HPOUT1L_ENA */
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#define WM8994_HPOUT1L_ENA 0x0200
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/* HPOUT1L_ENA */
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#define WM8994_HPOUT1L_ENA_MASK 0x0200
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/* HPOUT1R_ENA */
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#define WM8994_HPOUT1R_ENA 0x0100
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/* HPOUT1R_ENA */
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#define WM8994_HPOUT1R_ENA_MASK 0x0100
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/* VMID_SEL - [2:1] */
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#define WM8994_VMID_SEL_MASK 0x0006
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/* BIAS_ENA */
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#define WM8994_BIAS_ENA 0x0001
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/* BIAS_ENA */
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#define WM8994_BIAS_ENA_MASK 0x0001
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/*
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* R2 (0x02) - Power Management (2)
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*/
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/* OPCLK_ENA */
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#define WM8994_OPCLK_ENA 0x0800
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/*
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* R5 (0x05) - Power Management (5)
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*/
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/* AIF2DACL_ENA */
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#define WM8994_AIF2DACL_ENA 0x2000
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#define WM8994_AIF2DACL_ENA_MASK 0x2000
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/* AIF2DACR_ENA */
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#define WM8994_AIF2DACR_ENA 0x1000
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#define WM8994_AIF2DACR_ENA_MASK 0x1000
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/* DAC1L_ENA */
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#define WM8994_DAC1L_ENA 0x0002
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#define WM8994_DAC1L_ENA_MASK 0x0002
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/* DAC1R_ENA */
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#define WM8994_DAC1R_ENA 0x0001
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#define WM8994_DAC1R_ENA_MASK 0x0001
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/*
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* R45 (0x2D) - Output Mixer (1)
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*/
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/* DAC1L_TO_HPOUT1L */
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#define WM8994_DAC1L_TO_HPOUT1L 0x0100
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#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100
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/*
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* R46 (0x2E) - Output Mixer (2)
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*/
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/* DAC1R_TO_HPOUT1R */
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#define WM8994_DAC1R_TO_HPOUT1R 0x0100
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#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100
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/*
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* R76 (0x4C) - Charge Pump (1)
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*/
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/* CP_ENA */
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#define WM8994_CP_ENA 0x8000
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#define WM8994_CP_ENA_MASK 0x8000
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/*
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* R84 (0x54) - DC Servo (1)
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*/
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/* DCS_ENA_CHAN_1 */
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#define WM8994_DCS_ENA_CHAN_1 0x0002
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#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002
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/* DCS_ENA_CHAN_0 */
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#define WM8994_DCS_ENA_CHAN_0 0x0001
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#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001
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/*
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* R96 (0x60) - Analogue HP (1)
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*/
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/* HPOUT1L_RMV_SHORT */
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#define WM8994_HPOUT1L_RMV_SHORT 0x0080
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#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080
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/* HPOUT1L_OUTP */
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#define WM8994_HPOUT1L_OUTP 0x0040
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#define WM8994_HPOUT1L_OUTP_MASK 0x0040
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/* HPOUT1L_DLY */
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#define WM8994_HPOUT1L_DLY 0x0020
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#define WM8994_HPOUT1L_DLY_MASK 0x0020
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/* HPOUT1R_RMV_SHORT */
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#define WM8994_HPOUT1R_RMV_SHORT 0x0008
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#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008
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/* HPOUT1R_OUTP */
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#define WM8994_HPOUT1R_OUTP 0x0004
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#define WM8994_HPOUT1R_OUTP_MASK 0x0004
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/* HPOUT1R_DLY */
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#define WM8994_HPOUT1R_DLY 0x0002
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#define WM8994_HPOUT1R_DLY_MASK 0x0002
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/*
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* R512 (0x200) - AIF1 Clocking (1)
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*/
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/* AIF1CLK_SRC - [4:3] */
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#define WM8994_AIF1CLK_SRC_MASK 0x0018
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/* AIF1CLK_DIV */
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#define WM8994_AIF1CLK_DIV 0x0002
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/* AIF1CLK_ENA */
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#define WM8994_AIF1CLK_ENA 0x0001
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#define WM8994_AIF1CLK_ENA_MASK 0x0001
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/*
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* R517 (0x205) - AIF2 Clocking (2)
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*/
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/* AIF2DAC_DIV - [5:3] */
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#define WM8994_AIF2DAC_DIV_MASK 0x0038
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/*
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* R520 (0x208) - Clocking (1)
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*/
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/* AIF2DSPCLK_ENA */
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#define WM8994_AIF2DSPCLK_ENA 0x0004
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#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
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/* SYSDSPCLK_ENA */
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#define WM8994_SYSDSPCLK_ENA 0x0002
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#define WM8994_SYSDSPCLK_ENA_MASK 0x0002
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/* SYSCLK_SRC */
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#define WM8994_SYSCLK_SRC 0x0001
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/*
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* R521 (0x209) - Clocking (2)
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*/
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/* OPCLK_DIV - [2:0] */
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#define WM8994_OPCLK_DIV_MASK 0x0007
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/*
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* R528 (0x210) - AIF1 Rate
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*/
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/* AIF1_SR - [7:4] */
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#define WM8994_AIF1_SR_MASK 0x00F0
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#define WM8994_AIF1_SR_SHIFT 4
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/* AIF1CLK_RATE - [3:0] */
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#define WM8994_AIF1CLK_RATE_MASK 0x000F
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/*
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* R768 (0x300) - AIF1 Control (1)
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*/
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/* AIF1_BCLK_INV */
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#define WM8994_AIF1_BCLK_INV 0x0100
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/* AIF1_LRCLK_INV */
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#define WM8994_AIF1_LRCLK_INV 0x0080
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#define WM8994_AIF1_LRCLK_INV_MASK 0x0080
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/* AIF1_WL - [6:5] */
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#define WM8994_AIF1_WL_MASK 0x0060
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/* AIF1_FMT - [4:3] */
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#define WM8994_AIF1_FMT_MASK 0x0018
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/*
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* R769 (0x301) - AIF1 Control (2)
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*/
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/* AIF1_MONO */
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#define WM8994_AIF1_MONO 0x0100
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/*
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* R770 (0x302) - AIF1 Master/Slave
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*/
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/* AIF1_MSTR */
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#define WM8994_AIF1_MSTR 0x4000
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#define WM8994_AIF1_MSTR_MASK 0x4000
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/*
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* R771 (0x303) - AIF1 BCLK
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*/
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/* AIF1_BCLK_DIV - [8:4] */
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#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0
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#define WM8994_AIF1_BCLK_DIV_SHIFT 4
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/*
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* R1282 (0x502) - AIF2 DAC Left Volume
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*/
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/* AIF2DAC_VU */
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#define WM8994_AIF2DAC_VU 0x0100
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#define WM8994_AIF2DAC_VU_MASK 0x0100
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/* AIF2DACL_VOL - [7:0] */
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#define WM8994_AIF2DACL_VOL_MASK 0x00FF
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/*
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* R1283 (0x503) - AIF2 DAC Right Volume
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*/
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/* AIF2DACR_VOL - [7:0] */
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#define WM8994_AIF2DACR_VOL_MASK 0x00FF
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/*
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* R1312 (0x520) - AIF2 DAC Filters (1)
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*/
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/* AIF2DAC_MUTE */
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#define WM8994_AIF2DAC_MUTE_MASK 0x0200
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/*
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* R1537 (0x601) - DAC1 Left Mixer Routing
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*/
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/* AIF2DACL_TO_DAC1L */
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#define WM8994_AIF2DACL_TO_DAC1L 0x0004
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#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
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/*
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* R1538 (0x602) - DAC1 Right Mixer Routing
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*/
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/* AIF2DACR_TO_DAC1R */
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#define WM8994_AIF2DACR_TO_DAC1R 0x0004
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#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
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/*
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* R1552 (0x610) - DAC1 Left Volume
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*/
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/* DAC1L_MUTE */
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#define WM8994_DAC1L_MUTE_MASK 0x0200
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/* DAC1_VU */
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#define WM8994_DAC1_VU 0x0100
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#define WM8994_DAC1_VU_MASK 0x0100
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/* DAC1L_VOL - [7:0] */
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#define WM8994_DAC1L_VOL_MASK 0x00FF
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/*
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* R1553 (0x611) - DAC1 Right Volume
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*/
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/* DAC1R_MUTE */
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#define WM8994_DAC1R_MUTE_MASK 0x0200
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/* DAC1R_VOL - [7:0] */
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#define WM8994_DAC1R_VOL_MASK 0x00FF
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/*
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* GPIO
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*/
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/* OUTPUT PIN */
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#define WM8994_GPIO_DIR_OUTPUT 0x8000
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/* GPIO PIN MASK */
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#define WM8994_GPIO_DIR_MASK 0xFFE0
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/* I2S CLK */
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#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000
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/* GPn FN */
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#define WM8994_GPIO_FUNCTION_MASK 0x001F
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#endif
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