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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
184 lines
4.2 KiB
C
184 lines
4.2 KiB
C
/*
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* Mem setup common file for different types of DDR present on SMDK5250 boards.
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/spl.h>
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#include "clock_init.h"
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#include "common_setup.h"
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#include "exynos5_setup.h"
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#define ZQ_INIT_TIMEOUT 10000
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int dmc_config_zq(struct mem_timings *mem,
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struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val = 0;
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int i;
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/*
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* ZQ Calibration:
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* Select Driver Strength,
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* long calibration for manual calibration
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*/
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val = PHY_CON16_RESET_VAL;
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val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
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val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
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val |= ZQ_CLK_DIV_EN;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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/* Disable termination */
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if (mem->zq_mode_noterm)
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val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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/* ZQ_MANUAL_START: Enable */
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val |= ZQ_MANUAL_STR;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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/* ZQ_MANUAL_START: Disable */
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val &= ~ZQ_MANUAL_STR;
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/*
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* Since we are manaully calibrating the ZQ values,
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* we are looping for the ZQ_init to complete.
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*/
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i = ZQ_INIT_TIMEOUT;
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while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
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sdelay(100);
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i--;
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}
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if (!i)
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return -1;
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writel(val, &phy0_ctrl->phy_con16);
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i = ZQ_INIT_TIMEOUT;
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while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
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sdelay(100);
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i--;
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}
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if (!i)
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return -1;
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writel(val, &phy1_ctrl->phy_con16);
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return 0;
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}
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void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
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{
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unsigned long val;
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if (mode == DDR_MODE_DDR3) {
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val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
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writel(val, &dmc->phycontrol0);
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}
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/* Update DLL Information: Force DLL Resyncronization */
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val = readl(&dmc->phycontrol0);
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val |= FP_RSYNC;
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writel(val, &dmc->phycontrol0);
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/* Reset Force DLL Resyncronization */
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val = readl(&dmc->phycontrol0);
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val &= ~FP_RSYNC;
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writel(val, &dmc->phycontrol0);
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}
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void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
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{
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int channel, chip;
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for (channel = 0; channel < mem->dmc_channels; channel++) {
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unsigned long mask;
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mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
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for (chip = 0; chip < mem->chips_to_configure; chip++) {
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int i;
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mask |= chip << DIRECT_CMD_CHIP_SHIFT;
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/* Sending NOP command */
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writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
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/*
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* TODO(alim.akhtar@samsung.com): Do we need these
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* delays? This one and the next were not there for
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* DDR3.
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*/
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sdelay(0x10000);
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/* Sending EMRS/MRS commands */
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for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
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writel(mem->direct_cmd_msr[i] | mask,
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&dmc->directcmd);
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sdelay(0x10000);
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}
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if (mem->send_zq_init) {
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/* Sending ZQINIT command */
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writel(DIRECT_CMD_ZQINIT | mask,
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&dmc->directcmd);
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sdelay(10000);
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}
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}
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}
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}
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void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
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{
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int channel, chip;
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for (channel = 0; channel < mem->dmc_channels; channel++) {
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unsigned long mask;
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mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
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for (chip = 0; chip < mem->chips_per_channel; chip++) {
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mask |= chip << DIRECT_CMD_CHIP_SHIFT;
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/* PALL (all banks precharge) CMD */
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writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
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sdelay(0x10000);
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}
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}
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}
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void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
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{
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writel(mem->memconfig, &dmc->memconfig0);
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writel(mem->memconfig, &dmc->memconfig1);
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writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
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writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
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}
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void mem_ctrl_init(int reset)
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{
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struct spl_machine_param *param = spl_get_machine_params();
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struct mem_timings *mem;
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int ret;
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mem = clock_get_mem_timings();
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/* If there are any other memory variant, add their init call below */
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if (param->mem_type == DDR_MODE_DDR3) {
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ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
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if (ret) {
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/* will hang if failed to init memory control */
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while (1)
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;
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}
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} else {
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/* will hang if unknow memory type */
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while (1)
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;
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}
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}
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