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https://github.com/AsahiLinux/u-boot
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1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
265 lines
4.8 KiB
C
265 lines
4.8 KiB
C
/*
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* (C) Copyright 2012
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* Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <linux/errno.h>
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/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
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#define KM_XLX_PROGRAM_B_PIN 39
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#define BOCO_ADDR 0x10
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#define ID_REG 0x00
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#define BOCO2_ID 0x5b
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static int check_boco2(void)
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{
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int ret;
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u8 id;
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ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
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if (ret) {
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printf("%s: error reading the BOCO id !!\n", __func__);
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return ret;
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}
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return (id == BOCO2_ID);
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}
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static int boco_clear_bits(u8 reg, u8 flags)
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{
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int ret;
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u8 regval;
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/* give access to the EEPROM from FPGA */
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ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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regval &= ~flags;
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ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error writing the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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return 0;
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}
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static int boco_set_bits(u8 reg, u8 flags)
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{
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int ret;
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u8 regval;
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/* give access to the EEPROM from FPGA */
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ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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regval |= flags;
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ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error writing the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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return 0;
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}
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#define SPI_REG 0x06
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#define CFG_EEPROM 0x02
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#define FPGA_PROG 0x04
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#define FPGA_INIT_B 0x10
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#define FPGA_DONE 0x20
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static int fpga_done(void)
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{
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int ret = 0;
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u8 regval;
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/* this is only supported with the boco2 design */
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if (!check_boco2())
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return 0;
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ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, SPI_REG);
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return 0;
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}
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return regval & FPGA_DONE ? 1 : 0;
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}
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int skip;
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int trigger_fpga_config(void)
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{
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int ret = 0;
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/* if the FPGA is already configured, we do not want to
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* reconfigure it */
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skip = 0;
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if (fpga_done()) {
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printf("PCIe FPGA config: skipped\n");
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skip = 1;
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return 0;
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}
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if (check_boco2()) {
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/* we have a BOCO2, this has to be triggered here */
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/* make sure the FPGA_can access the EEPROM */
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ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
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if (ret)
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return ret;
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/* trigger the config start */
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ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
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if (ret)
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return ret;
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/* small delay for the pulse */
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udelay(10);
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/* up signal for pulse end */
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ret = boco_set_bits(SPI_REG, FPGA_PROG);
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if (ret)
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return ret;
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/* finally, raise INIT_B to remove the config delay */
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ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
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if (ret)
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return ret;
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} else {
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/* we do it the old way, with the gpio pin */
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kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
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kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
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/* small delay for the pulse */
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udelay(10);
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kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
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}
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return 0;
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}
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int wait_for_fpga_config(void)
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{
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int ret = 0;
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u8 spictrl;
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u32 timeout = 20000;
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if (skip)
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return 0;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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printf("PCIe FPGA config:");
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do {
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ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
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if (ret) {
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printf("%s: error reading the BOCO spictrl !!\n",
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__func__);
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return ret;
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}
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if (timeout-- == 0) {
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printf(" FPGA_DONE timeout\n");
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return -EFAULT;
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}
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udelay(10);
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} while (!(spictrl & FPGA_DONE));
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printf(" done\n");
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return 0;
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}
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#if defined(KM_PCIE_RESET_MPP7)
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#define KM_PEX_RST_GPIO_PIN 7
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int fpga_reset(void)
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{
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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printf("PCIe reset through GPIO7: ");
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/* apply PCIe reset via GPIO */
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kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
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kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
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kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
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udelay(1000*10);
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kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
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printf(" done\n");
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return 0;
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}
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#else
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#define PRST1 0x4
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#define PCIE_RST 0x10
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#define TRAFFIC_RST 0x04
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int fpga_reset(void)
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{
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int ret = 0;
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u8 resets;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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/* if we have skipped, we only want to reset the PCIe part */
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resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
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ret = boco_clear_bits(PRST1, resets);
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if (ret)
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return ret;
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/* small delay for the pulse */
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udelay(10);
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ret = boco_set_bits(PRST1, resets);
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if (ret)
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return ret;
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return 0;
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}
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#endif
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/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
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* is available from the Bobcat SPI bus */
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int toggle_eeprom_spi_bus(void)
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{
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int ret = 0;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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ret = boco_set_bits(SPI_REG, CFG_EEPROM);
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if (ret)
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return ret;
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return 0;
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}
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