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c9a8b25ef9
Make the I2C2 and I2C1 use the same initialize codes. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
495 lines
12 KiB
C
495 lines
12 KiB
C
/*
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* Copyright 2006,2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_HARD_I2C
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#include <command.h>
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#include <i2c.h> /* Functional interface */
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#include <asm/io.h>
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#include <asm/fsl_i2c.h> /* HW definitions */
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/* The maximum number of microseconds we will wait until another master has
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* released the bus. If not defined in the board header file, then use a
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* generic value.
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*/
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#ifndef CONFIG_I2C_MBB_TIMEOUT
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#define CONFIG_I2C_MBB_TIMEOUT 100000
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#endif
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/* The maximum number of microseconds we will wait for a read or write
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* operation to complete. If not defined in the board header file, then use a
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* generic value.
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*/
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#ifndef CONFIG_I2C_TIMEOUT
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#define CONFIG_I2C_TIMEOUT 10000
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#endif
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#define I2C_READ_BIT 1
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#define I2C_WRITE_BIT 0
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DECLARE_GLOBAL_DATA_PTR;
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the global variables.
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*/
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#ifndef CONFIG_SYS_SPD_BUS_NUM
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#endif
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static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
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#if defined(CONFIG_I2C_MUX)
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static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
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#endif
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static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
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static const struct fsl_i2c *i2c_dev[2] = {
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(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
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#ifdef CONFIG_SYS_I2C2_OFFSET
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(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
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#endif
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};
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/* I2C speed map for a DFSR value of 1 */
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/*
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* Map I2C frequency dividers to FDR and DFSR values
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*
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* This structure is used to define the elements of a table that maps I2C
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* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
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* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
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* Sampling Rate (DFSR) registers.
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*
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* The actual table should be defined in the board file, and it must be called
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* fsl_i2c_speed_map[].
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*
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* The last entry of the table must have a value of {-1, X}, where X is same
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* FDR/DFSR values as the second-to-last entry. This guarantees that any
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* search through the array will always find a match.
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*
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* The values of the divider must be in increasing numerical order, i.e.
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* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
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*
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* For this table, the values are based on a value of 1 for the DFSR
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* register. See the application note AN2919 "Determining the I2C Frequency
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* Divider Ratio for SCL"
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*
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* ColdFire I2C frequency dividers for FDR values are different from
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* PowerPC. The protocol to use the I2C module is still the same.
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* A different table is defined and are based on MCF5xxx user manual.
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*
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*/
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static const struct {
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unsigned short divider;
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u8 fdr;
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} fsl_i2c_speed_map[] = {
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#ifdef __M68K__
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{20, 32}, {22, 33}, {24, 34}, {26, 35},
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{28, 0}, {28, 36}, {30, 1}, {32, 37},
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{34, 2}, {36, 38}, {40, 3}, {40, 39},
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{44, 4}, {48, 5}, {48, 40}, {56, 6},
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{56, 41}, {64, 42}, {68, 7}, {72, 43},
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{80, 8}, {80, 44}, {88, 9}, {96, 41},
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{104, 10}, {112, 42}, {128, 11}, {128, 43},
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{144, 12}, {160, 13}, {160, 48}, {192, 14},
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{192, 49}, {224, 50}, {240, 15}, {256, 51},
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{288, 16}, {320, 17}, {320, 52}, {384, 18},
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{384, 53}, {448, 54}, {480, 19}, {512, 55},
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{576, 20}, {640, 21}, {640, 56}, {768, 22},
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{768, 57}, {960, 23}, {896, 58}, {1024, 59},
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{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
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{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
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{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
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{-1, 31}
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#endif
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};
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/**
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* Set the I2C bus speed for a given I2C device
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*
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* @param dev: the I2C device
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* @i2c_clk: I2C bus clock frequency
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* @speed: the desired speed of the bus
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*
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* The I2C device must be stopped before calling this function.
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*
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* The return value is the actual bus speed that is set.
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*/
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static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
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unsigned int i2c_clk, unsigned int speed)
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{
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unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed. That means that we
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* want the first divider that is equal to or greater than the
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* calculated divider.
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*/
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#ifdef __PPC__
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u8 dfsr, fdr = 0x31; /* Default if no FDR found */
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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
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unsigned short a, b, ga, gb;
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unsigned long c_div, est_div;
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#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
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dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
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#else
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/* Condition 1: dfsr <= 50/T */
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dfsr = (5 * (i2c_clk / 1000)) / 100000;
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#endif
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#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
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fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
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speed = i2c_clk / divider; /* Fake something */
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#else
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debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
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if (!dfsr)
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dfsr = 1;
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est_div = ~0;
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for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
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for (gb = 0; gb < 8; gb++) {
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b = 16 << gb;
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c_div = b * (a + ((3*dfsr)/b)*2);
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if ((c_div > divider) && (c_div < est_div)) {
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unsigned short bin_gb, bin_ga;
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est_div = c_div;
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bin_gb = gb << 2;
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bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
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fdr = bin_gb | bin_ga;
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speed = i2c_clk / est_div;
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debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
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"a:%d, b:%d, speed:%d\n",
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fdr, est_div, ga, gb, a, b, speed);
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/* Condition 2 not accounted for */
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debug("Tr <= %d ns\n",
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(b - 3 * dfsr) * 1000000 /
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(i2c_clk / 1000));
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}
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}
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if (a == 20)
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a += 2;
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if (a == 24)
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a += 4;
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}
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debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
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debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
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#endif
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writeb(dfsr, &dev->dfsrr); /* set default filter */
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writeb(fdr, &dev->fdr); /* set bus speed */
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#else
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
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if (fsl_i2c_speed_map[i].divider >= divider) {
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u8 fdr;
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fdr = fsl_i2c_speed_map[i].fdr;
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speed = i2c_clk / fsl_i2c_speed_map[i].divider;
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writeb(fdr, &dev->fdr); /* set bus speed */
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break;
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}
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#endif
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return speed;
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}
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unsigned int get_i2c_clock(int bus)
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{
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if (bus)
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return gd->i2c2_clk; /* I2C2 clock */
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else
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return gd->i2c1_clk; /* I2C1 clock */
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}
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void
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i2c_init(int speed, int slaveadd)
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{
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struct fsl_i2c *dev;
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unsigned int temp;
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int bus_num, i;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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#ifdef CONFIG_SYS_I2C2_OFFSET
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bus_num = 2;
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#else
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bus_num = 1;
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#endif
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for (i = 0; i < bus_num; i++) {
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dev = i2c_dev[i];
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writeb(0, &dev->cr); /* stop I2C controller */
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udelay(5); /* let it shutdown in peace */
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temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
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if (gd->flags & GD_FLG_RELOC)
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i2c_bus_speed[i] = temp;
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writeb(slaveadd << 1, &dev->adr);/* write slave address */
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writeb(0x0, &dev->sr); /* clear status register */
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writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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}
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#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
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/* Call board specific i2c bus reset routine AFTER the bus has been
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* initialized. Use either this callpoint or i2c_init_board;
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* which is called before i2c_init operations.
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* For details about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_board_late_init();
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#endif
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}
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static int
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i2c_wait4bus(void)
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{
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unsigned long long timeval = get_ticks();
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
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while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
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if ((get_ticks() - timeval) > timeout)
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return -1;
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}
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return 0;
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}
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static __inline__ int
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i2c_wait(int write)
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{
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u32 csr;
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unsigned long long timeval = get_ticks();
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
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do {
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csr = readb(&i2c_dev[i2c_bus_num]->sr);
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if (!(csr & I2C_SR_MIF))
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continue;
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/* Read again to allow register to stabilise */
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csr = readb(&i2c_dev[i2c_bus_num]->sr);
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writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
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if (csr & I2C_SR_MAL) {
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debug("i2c_wait: MAL\n");
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return -1;
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}
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if (!(csr & I2C_SR_MCF)) {
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debug("i2c_wait: unfinished\n");
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return -1;
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}
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
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debug("i2c_wait: No RXACK\n");
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return -1;
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}
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return 0;
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} while ((get_ticks() - timeval) < timeout);
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debug("i2c_wait: timed out\n");
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return -1;
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}
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static __inline__ int
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i2c_write_addr (u8 dev, u8 dir, int rsta)
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{
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
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| (rsta ? I2C_CR_RSTA : 0),
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&i2c_dev[i2c_bus_num]->cr);
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writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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return 0;
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return 1;
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}
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static __inline__ int
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__i2c_write(u8 *data, int length)
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{
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int i;
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for (i = 0; i < length; i++) {
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writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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break;
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}
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return i;
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}
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static __inline__ int
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__i2c_read(u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
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&i2c_dev[i2c_bus_num]->cr);
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/* dummy read */
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readb(&i2c_dev[i2c_bus_num]->dr);
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for (i = 0; i < length; i++) {
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if (i2c_wait(I2C_READ_BIT) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
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&i2c_dev[i2c_bus_num]->cr);
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/* Do not generate stop on last byte */
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if (i == length - 1)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
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&i2c_dev[i2c_bus_num]->cr);
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data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
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}
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return i;
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}
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int
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i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen)
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i = 0; /* No error so far */
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if (length
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&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
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i = __i2c_read(data, length);
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i2c_wait4bus()) /* Wait until STOP */
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debug("i2c_read: wait4bus timed out\n");
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen) {
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i = __i2c_write(data, length);
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}
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i2c_wait4bus()) /* Wait until STOP */
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debug("i2c_write: wait4bus timed out\n");
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_probe(uchar chip)
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{
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/* For unknow reason the controller will ACK when
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* probing for a slave with the same address, so skip
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* it.
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*/
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if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
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return -1;
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return i2c_read(chip, 0, 0, NULL, 0);
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}
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int i2c_set_bus_num(unsigned int bus)
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{
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#if defined(CONFIG_I2C_MUX)
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if (bus < CONFIG_SYS_MAX_I2C_BUS) {
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i2c_bus_num = bus;
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} else {
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int ret;
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ret = i2x_mux_select_mux(bus);
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if (ret)
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return ret;
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i2c_bus_num = 0;
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}
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i2c_bus_num_mux = bus;
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#else
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#ifdef CONFIG_SYS_I2C2_OFFSET
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if (bus > 1) {
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#else
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if (bus > 0) {
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#endif
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return -1;
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}
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i2c_bus_num = bus;
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#endif
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return 0;
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}
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int i2c_set_bus_speed(unsigned int speed)
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{
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unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
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writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
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i2c_bus_speed[i2c_bus_num] =
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set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
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|
|
|
return 0;
|
|
}
|
|
|
|
unsigned int i2c_get_bus_num(void)
|
|
{
|
|
#if defined(CONFIG_I2C_MUX)
|
|
return i2c_bus_num_mux;
|
|
#else
|
|
return i2c_bus_num;
|
|
#endif
|
|
}
|
|
|
|
unsigned int i2c_get_bus_speed(void)
|
|
{
|
|
return i2c_bus_speed[i2c_bus_num];
|
|
}
|
|
|
|
#endif /* CONFIG_HARD_I2C */
|