mirror of
https://github.com/AsahiLinux/u-boot
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4727f954a4
Add Flexcom8 node with required referenced nodes as phandles. Since Flexcom8 is present in Linux, take the node exactly as-is from Linux. Some nodes are referenced in Linux as phandles, the dma and the gic. Add them as well to the file, even if they are unused by Uboot. This is a step towards having the U-boot DT equivalent with the DT in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
246 lines
6.6 KiB
Text
246 lines
6.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clk/at91.h>
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#include <dt-bindings/dma/at91.h>
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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interrupt-parent = <&gic>;
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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pioA: pinctrl@e0014000 {
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compatible = "microchip,sama7g5-gpio";
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reg = <0xe0014000 0x800>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
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status = "okay";
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pinctrl: pinctrl_default {
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compatible = "microchip,sama7g5-pinctrl";
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};
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};
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pmc: pmc@e0018000 {
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compatible = "microchip,sama7g5-pmc";
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reg = <0xe0018000 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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status = "okay";
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};
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clk32: sckc@e001d050 {
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compatible = "microchip,sam9x60-sckc";
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reg = <0xe001d050 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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qspi0: spi@e080c000 {
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compatible = "microchip,sama7g5-ospi";
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reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi1: spi@e0810000 {
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compatible = "microchip,sama7g5-qspi";
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reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sdmmc0: sdio-host@e1204000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1204000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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status = "disabled";
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};
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sdmmc1: sdio-host@e1208000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1208000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7g5-pit64b";
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reg = <0xe1800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
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clock-names = "pclk", "gclk";
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status = "okay";
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};
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flx1: flexcom@e181c000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe181c000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe181c000 0x800>;
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status = "disabled";
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i2c1: i2c@600 {
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compatible = "atmel,sama5d2-i2c";
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reg = <0x600 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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};
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};
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uart0: serial@e1824200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xe1824200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usart";
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status = "disabled";
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};
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gmac0: ethernet@e2800000 {
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compatible = "cdns,sama7g5-gem";
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reg = <0xe2800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
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clock-names = "hclk", "pclk", "tx_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
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assigned-clock-rates = <125000000>;
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status = "disabled";
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};
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gmac1: ethernet@e2804000 {
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compatible = "cdns,sama7g5-emac";
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reg = <0xe2804000 0x1000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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dma0: dma-controller@e2808000 {
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compatible = "microchip,sama7g5-dma";
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reg = <0xe2808000 0x1000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
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clock-names = "dma_clk";
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status = "disabled";
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};
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flx8: flexcom@e2818000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe2818000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2818000 0x800>;
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status = "disabled";
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i2c8: i2c@600 {
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compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
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atmel,fifo-size = <32>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
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<&dma0 AT91_XDMAC_DT_PERID(22)>;
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dma-names = "rx", "tx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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gic: interrupt-controller@e8c11000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupt-parent;
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reg = <0xe8c11000 0x1000>,
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<0xe8c12000 0x2000>;
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};
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};
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};
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};
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