mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 23:21:01 +00:00
3b82335015
On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default). To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399 populate R392-R395, R299, R300). So we add new DTS file and new defconfig dedicated for QSPI. Other changes to support the DM QSPI: - Add QSPI node and alias spi0. - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req conflict - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to align with kernel and also present the conflict. - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to "spi-flash" - Remove iomux settings of qspi in board codes which is not needed for DM driver. Signed-off-by: Ye Li <ye.li@nxp.com>
400 lines
9.5 KiB
Text
400 lines
9.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "Freescale i.MX7 SabreSD Board";
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compatible = "fsl,imx7d-sdb", "fsl,imx7d";
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aliases {
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spi5 = &soft_spi;
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};
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memory {
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reg = <0x80000000 0x80000000>;
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};
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soft_spi: soft-spi {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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status = "okay";
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gpio-sck = <&gpio1 13 0>;
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gpio-mosi = <&gpio1 9 0>;
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cs-gpios = <&gpio1 12 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio_spi: gpio_spi@0 {
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compatible = "fairchild,74hc595";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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registers-number = <1>;
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registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
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spi-max-frequency = <100000>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_sd1_vmmc: regulator@3 {
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compatible = "regulator-fixed";
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regulator-name = "VDD_SD1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <200000>;
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enable-active-high;
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};
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};
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};
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&iomuxc {
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imx7d-sdb {
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pinctrl_spi1: spi1grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
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MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
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MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
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>;
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};
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pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
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fsl,pins = <
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
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MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
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MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x59
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MX7D_PAD_SD1_CLK__SD1_CLK 0x19
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
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MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
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MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX7D_PAD_SD2_CMD__SD2_CMD 0x59
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MX7D_PAD_SD2_CLK__SD2_CLK 0x19
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MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
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MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
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MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
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MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
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MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */
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MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
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fsl,pins = <
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MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
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MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
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MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
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MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
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MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
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MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
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fsl,pins = <
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MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
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MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
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MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
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MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
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MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
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MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59
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MX7D_PAD_SD3_CLK__SD3_CLK 0x19
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
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>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze3000@08 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_sd1_vmmc>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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non-removable;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "okay";
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};
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