mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
0c1456d571
When a crash occurs in thumb mode the crash dump is incorrect. This is due to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in the definition of macro thumb_mode(regs). Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt. With the patch crash dumps indicate thumb mode correctly. On a system with thumb mode: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 The Flags line has '(T)' and in the Code line the output is in u16 groups. On a system without thumb mode: => exception breakpoint prefetch abort pc : [<7ff5a5c8>] lr : [<7ff675ec>] reloc pc : [<0000e5c8>] lr : [<0001b5ec>] sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214 r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000 r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e) The Flags line does not show '(T)' and in the Code line the output is in u32 groups. Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Marek Vasut <marex@denx.de>
131 lines
2.7 KiB
C
131 lines
2.7 KiB
C
/*
|
|
* linux/include/asm-arm/proc-armv/ptrace.h
|
|
*
|
|
* Copyright (C) 1996-1999 Russell King
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#ifndef __ASM_PROC_PTRACE_H
|
|
#define __ASM_PROC_PTRACE_H
|
|
|
|
#ifdef CONFIG_ARM64
|
|
|
|
#define PCMASK 0
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/*
|
|
* This struct defines the way the registers are stored
|
|
* on the stack during an exception.
|
|
*/
|
|
struct pt_regs {
|
|
unsigned long elr;
|
|
unsigned long regs[31];
|
|
};
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#else /* CONFIG_ARM64 */
|
|
|
|
#define USR26_MODE 0x00
|
|
#define FIQ26_MODE 0x01
|
|
#define IRQ26_MODE 0x02
|
|
#define SVC26_MODE 0x03
|
|
#define USR_MODE 0x10
|
|
#define FIQ_MODE 0x11
|
|
#define IRQ_MODE 0x12
|
|
#define SVC_MODE 0x13
|
|
#define MON_MODE 0x16
|
|
#define ABT_MODE 0x17
|
|
#define HYP_MODE 0x1a
|
|
#define UND_MODE 0x1b
|
|
#define SYSTEM_MODE 0x1f
|
|
#define MODE_MASK 0x1f
|
|
#define T_BIT 0x20
|
|
#define F_BIT 0x40
|
|
#define I_BIT 0x80
|
|
#define A_BIT 0x100
|
|
#define CC_V_BIT (1 << 28)
|
|
#define CC_C_BIT (1 << 29)
|
|
#define CC_Z_BIT (1 << 30)
|
|
#define CC_N_BIT (1 << 31)
|
|
#define PCMASK 0
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/* this struct defines the way the registers are stored on the
|
|
stack during a system call. */
|
|
|
|
struct pt_regs {
|
|
long uregs[18];
|
|
};
|
|
|
|
#define ARM_cpsr uregs[16]
|
|
#define ARM_pc uregs[15]
|
|
#define ARM_lr uregs[14]
|
|
#define ARM_sp uregs[13]
|
|
#define ARM_ip uregs[12]
|
|
#define ARM_fp uregs[11]
|
|
#define ARM_r10 uregs[10]
|
|
#define ARM_r9 uregs[9]
|
|
#define ARM_r8 uregs[8]
|
|
#define ARM_r7 uregs[7]
|
|
#define ARM_r6 uregs[6]
|
|
#define ARM_r5 uregs[5]
|
|
#define ARM_r4 uregs[4]
|
|
#define ARM_r3 uregs[3]
|
|
#define ARM_r2 uregs[2]
|
|
#define ARM_r1 uregs[1]
|
|
#define ARM_r0 uregs[0]
|
|
#define ARM_ORIG_r0 uregs[17]
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
#define user_mode(regs) \
|
|
(((regs)->ARM_cpsr & 0xf) == 0)
|
|
|
|
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
|
|
#define thumb_mode(regs) \
|
|
(((regs)->ARM_cpsr & T_BIT))
|
|
#else
|
|
#define thumb_mode(regs) (0)
|
|
#endif
|
|
|
|
#define processor_mode(regs) \
|
|
((regs)->ARM_cpsr & MODE_MASK)
|
|
|
|
#define interrupts_enabled(regs) \
|
|
(!((regs)->ARM_cpsr & I_BIT))
|
|
|
|
#define fast_interrupts_enabled(regs) \
|
|
(!((regs)->ARM_cpsr & F_BIT))
|
|
|
|
#define condition_codes(regs) \
|
|
((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
|
|
|
|
/* Are the current registers suitable for user mode?
|
|
* (used to maintain security in signal handlers)
|
|
*/
|
|
static inline int valid_user_regs(struct pt_regs *regs)
|
|
{
|
|
if ((regs->ARM_cpsr & 0xf) == 0 &&
|
|
(regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
|
|
return 1;
|
|
|
|
/*
|
|
* Force CPSR to something logical...
|
|
*/
|
|
regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* CONFIG_ARM64 */
|
|
|
|
#endif
|