mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
62f96866d3
Synchronise device tree with linux v6.1-rc3. Note: Nowadays, the intent is for them regular device trees to just be synchronised from them Linux kernel device trees and any and all U-Boot specific changes need to go into the -u-boot.dtsi device tree include files which BTW get included automatically by the U-Boot build system. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright(C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
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#define __DT_BINDINGS_CLOCK_IMXRT1050_H
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#define IMXRT1050_CLK_DUMMY 0
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#define IMXRT1050_CLK_CKIL 1
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#define IMXRT1050_CLK_CKIH 2
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#define IMXRT1050_CLK_OSC 3
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#define IMXRT1050_CLK_PLL2_PFD0_352M 4
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#define IMXRT1050_CLK_PLL2_PFD1_594M 5
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#define IMXRT1050_CLK_PLL2_PFD2_396M 6
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#define IMXRT1050_CLK_PLL3_PFD0_720M 7
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#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
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#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
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#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
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#define IMXRT1050_CLK_PLL2_198M 11
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#define IMXRT1050_CLK_PLL3_120M 12
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#define IMXRT1050_CLK_PLL3_80M 13
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#define IMXRT1050_CLK_PLL3_60M 14
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#define IMXRT1050_CLK_PLL1_BYPASS 15
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#define IMXRT1050_CLK_PLL2_BYPASS 16
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#define IMXRT1050_CLK_PLL3_BYPASS 17
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#define IMXRT1050_CLK_PLL5_BYPASS 19
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#define IMXRT1050_CLK_PLL1_REF_SEL 20
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#define IMXRT1050_CLK_PLL2_REF_SEL 21
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#define IMXRT1050_CLK_PLL3_REF_SEL 22
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#define IMXRT1050_CLK_PLL5_REF_SEL 23
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#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
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#define IMXRT1050_CLK_PERIPH_SEL 25
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#define IMXRT1050_CLK_SEMC_ALT_SEL 26
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#define IMXRT1050_CLK_SEMC_SEL 27
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#define IMXRT1050_CLK_USDHC1_SEL 28
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#define IMXRT1050_CLK_USDHC2_SEL 29
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#define IMXRT1050_CLK_LPUART_SEL 30
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#define IMXRT1050_CLK_LCDIF_SEL 31
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#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
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#define IMXRT1050_CLK_VIDEO_DIV 33
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#define IMXRT1050_CLK_ARM_PODF 34
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#define IMXRT1050_CLK_LPUART_PODF 35
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#define IMXRT1050_CLK_USDHC1_PODF 36
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#define IMXRT1050_CLK_USDHC2_PODF 37
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#define IMXRT1050_CLK_SEMC_PODF 38
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#define IMXRT1050_CLK_AHB_PODF 39
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#define IMXRT1050_CLK_LCDIF_PRED 40
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#define IMXRT1050_CLK_LCDIF_PODF 41
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#define IMXRT1050_CLK_USDHC1 42
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#define IMXRT1050_CLK_USDHC2 43
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#define IMXRT1050_CLK_LPUART1 44
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#define IMXRT1050_CLK_SEMC 45
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#define IMXRT1050_CLK_LCDIF_APB 46
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#define IMXRT1050_CLK_PLL1_ARM 47
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#define IMXRT1050_CLK_PLL2_SYS 48
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#define IMXRT1050_CLK_PLL3_USB_OTG 49
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#define IMXRT1050_CLK_PLL4_AUDIO 50
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#define IMXRT1050_CLK_PLL5_VIDEO 51
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#define IMXRT1050_CLK_PLL6_ENET 52
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#define IMXRT1050_CLK_PLL7_USB_HOST 53
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#define IMXRT1050_CLK_LCDIF_PIX 54
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#define IMXRT1050_CLK_USBOH3 55
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#define IMXRT1050_CLK_IPG_PDOF 56
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#define IMXRT1050_CLK_PER_CLK_SEL 57
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#define IMXRT1050_CLK_PER_PDOF 58
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#define IMXRT1050_CLK_DMA 59
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#define IMXRT1050_CLK_DMA_MUX 60
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#define IMXRT1050_CLK_END 61
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#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
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