mirror of
https://github.com/AsahiLinux/u-boot
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e327e2affd
With CONFIG_DM_USB_GADGET=y, we no longer need any board_usb_*() logic
because:
* the dwc2 driver is DM compatible, and handles its own clock enabling
* the dwc3-meson-gxl glue drivers handles "force mode switching"
Remove all mach-meson gx & axg usb code and enable CONFIG_DM_USB_GADGET.
Note: Only configs having both CONFIG_USB_DWC3_MESON_GXL=y *and*
USB_GADGET_DWC2_OTG=y have been updated.
Thanks for the original work from Mattijs at [1]
[1] https://lore.kernel.org/all/20221024-meson-dm-usb-v1-2-2ab077a503b9@baylibre.com/
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230117-u-boot-usb-gxl-otg-dm-v1-2-2853f6d75b06@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
104 lines
2.6 KiB
C
104 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
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* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <asm/arch/boot.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/meson-vpu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int meson_get_boot_device(void)
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{
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return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
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}
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/* Configure the reserved memory zones exported by the secure registers
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* into EFI and DTB reserved memory entries.
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*/
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void meson_init_reserved_memory(void *fdt)
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{
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u64 bl31_size, bl31_start;
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u64 bl32_size, bl32_start;
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u32 reg;
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/*
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* Get ARM Trusted Firmware reserved memory zones in :
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* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
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* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
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* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
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*/
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reg = readl(GX_AO_SEC_GP_CFG3);
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bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
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>> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
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bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
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bl31_start = readl(GX_AO_SEC_GP_CFG5);
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bl32_start = readl(GX_AO_SEC_GP_CFG4);
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/*
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* Early Meson GX Firmware revisions did not provide the reserved
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* memory zones in the registers, keep fixed memory zone handling.
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*/
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if (IS_ENABLED(CONFIG_MESON_GX) &&
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!reg && !bl31_start && !bl32_start) {
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bl31_start = 0x10000000;
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bl31_size = 0x200000;
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}
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/* Add first 16MiB reserved zone */
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meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
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/* Add BL31 reserved zone */
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if (bl31_start && bl31_size)
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meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
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/* Add BL32 reserved zone */
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if (bl32_start && bl32_size)
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meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
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#if defined(CONFIG_VIDEO_MESON)
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meson_vpu_rsv_fb(fdt);
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#endif
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}
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phys_size_t get_effective_memsize(void)
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{
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/* Size is reported in MiB, convert it in bytes */
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return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
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>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
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}
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static struct mm_region gx_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xc0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xc0000000UL,
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.phys = 0xc0000000UL,
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.size = 0x30000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = gx_mem_map;
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